recuart.fit.eqn

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--rbr[0] is rbr[0] at LC_X2_Y4_N4
--operation mode is normal

rbr[0]_lut_out = GND;
rbr[0] = DFFEAS(rbr[0]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, rsr[0], , , VCC);


--rbr[1] is rbr[1] at LC_X2_Y4_N9
--operation mode is normal

rbr[1]_lut_out = GND;
rbr[1] = DFFEAS(rbr[1]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, rsr[1], , , VCC);


--rbr[2] is rbr[2] at LC_X2_Y3_N2
--operation mode is normal

rbr[2]_lut_out = GND;
rbr[2] = DFFEAS(rbr[2]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, rsr[2], , , VCC);


--rbr[3] is rbr[3] at LC_X2_Y3_N3
--operation mode is normal

rbr[3]_lut_out = GND;
rbr[3] = DFFEAS(rbr[3]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, rsr[3], , , VCC);


--rbr[4] is rbr[4] at LC_X2_Y3_N4
--operation mode is normal

rbr[4]_lut_out = GND;
rbr[4] = DFFEAS(rbr[4]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, rsr[4], , , VCC);


--rbr[5] is rbr[5] at LC_X2_Y3_N5
--operation mode is normal

rbr[5]_lut_out = GND;
rbr[5] = DFFEAS(rbr[5]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, rsr[5], , , VCC);


--rbr[6] is rbr[6] at LC_X2_Y3_N9
--operation mode is normal

rbr[6]_lut_out = rsr[6];
rbr[6] = DFFEAS(rbr[6]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, , , , );


--rbr[7] is rbr[7] at LC_X2_Y3_N6
--operation mode is normal

rbr[7]_lut_out = GND;
rbr[7] = DFFEAS(rbr[7]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L58, rsr[7], , , VCC);


--A1L05Q is data_ready~reg0 at LC_X4_Y2_N5
--operation mode is normal

A1L05Q_lut_out = VCC;
A1L05Q = DFFEAS(A1L05Q_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , A1L48, , , , );


--A1L26Q is framing_error~reg0 at LC_X2_Y2_N2
--operation mode is normal

A1L26Q_lut_out = rxd2 & !no_bits_rcvd[0] & A1L68;
A1L26Q = DFFEAS(A1L26Q_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L16, , , , );


--A1L27Q is parity_error~reg0 at LC_X4_Y4_N3
--operation mode is normal

A1L27Q_lut_out = VCC;
A1L27Q = DFFEAS(A1L27Q_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L17, , , , );


--rsr[0] is rsr[0] at LC_X2_Y2_N6
--operation mode is normal

rsr[0]_lut_out = !rxd2;
rsr[0] = DFFEAS(rsr[0]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, , , , );


--clkdiv[3] is clkdiv[3] at LC_X3_Y3_N2
--operation mode is normal

clkdiv[3]_lut_out = !clkdiv[3];
clkdiv[3] = DFFEAS(clkdiv[3]_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , A1L84, , , , );


--no_bits_rcvd[2] is no_bits_rcvd[2] at LC_X5_Y2_N9
--operation mode is normal

no_bits_rcvd[2]_lut_out = !no_bits_rcvd[2];
no_bits_rcvd[2] = DFFEAS(no_bits_rcvd[2]_lut_out, GLOBAL(clkdiv[3]), !A1L86, , A1L1, , , , );


--no_bits_rcvd[1] is no_bits_rcvd[1] at LC_X3_Y2_N8
--operation mode is normal

no_bits_rcvd[1]_lut_out = !no_bits_rcvd[1];
no_bits_rcvd[1] = DFFEAS(no_bits_rcvd[1]_lut_out, GLOBAL(clkdiv[3]), !A1L86, , no_bits_rcvd[0], , , , );


--no_bits_rcvd[0] is no_bits_rcvd[0] at LC_X6_Y2_N3
--operation mode is normal

no_bits_rcvd[0]_lut_out = !no_bits_rcvd[0];
no_bits_rcvd[0] = DFFEAS(no_bits_rcvd[0]_lut_out, GLOBAL(clkdiv[3]), !A1L86, , , , , , );


--no_bits_rcvd[3] is no_bits_rcvd[3] at LC_X4_Y2_N9
--operation mode is normal

no_bits_rcvd[3]_lut_out = !no_bits_rcvd[3];
no_bits_rcvd[3] = DFFEAS(no_bits_rcvd[3]_lut_out, GLOBAL(clkdiv[3]), !A1L86, , A1L2, , , , );


--A1L58 is reduce_nor~73 at LC_X3_Y2_N1
--operation mode is normal

A1L58 = !no_bits_rcvd[1] & no_bits_rcvd[0] & no_bits_rcvd[3] & !no_bits_rcvd[2];


--rsr[1] is rsr[1] at LC_X2_Y2_N3
--operation mode is normal

rsr[1]_lut_out = GND;
rsr[1] = DFFEAS(rsr[1]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, rsr[0], , , VCC);


--rsr[2] is rsr[2] at LC_X2_Y2_N4
--operation mode is normal

rsr[2]_lut_out = GND;
rsr[2] = DFFEAS(rsr[2]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, rsr[1], , , VCC);


--rsr[3] is rsr[3] at LC_X2_Y2_N1
--operation mode is normal

rsr[3]_lut_out = GND;
rsr[3] = DFFEAS(rsr[3]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, rsr[2], , , VCC);


--rsr[4] is rsr[4] at LC_X2_Y2_N7
--operation mode is normal

rsr[4]_lut_out = GND;
rsr[4] = DFFEAS(rsr[4]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, rsr[3], , , VCC);


--rsr[5] is rsr[5] at LC_X2_Y2_N0
--operation mode is normal

rsr[5]_lut_out = GND;
rsr[5] = DFFEAS(rsr[5]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, rsr[4], , , VCC);


--rsr[6] is rsr[6] at LC_X2_Y2_N5
--operation mode is normal

rsr[6]_lut_out = rsr[5];
rsr[6] = DFFEAS(rsr[6]_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, , , , );


--clk16x is clk16x at LC_X2_Y1_N8
--operation mode is normal

clk16x_lut_out = !clk16x;
clk16x = DFFEAS(clk16x_lut_out, GLOBAL(clk), !GLOBAL(rst), , A1L38, , , , );


--A1L48 is reduce_nor~2 at LC_X4_Y2_N3
--operation mode is normal

A1L48 = no_bits_rcvd[1] & no_bits_rcvd[3] & !no_bits_rcvd[2] & no_bits_rcvd[0];


--A1L68 is reduce_nor~74 at LC_X3_Y2_N5
--operation mode is normal

A1L68 = no_bits_rcvd[1] & (no_bits_rcvd[3] & !no_bits_rcvd[2]);


--rxd2 is rxd2 at LC_X5_Y2_N2
--operation mode is normal

rxd2_lut_out = rxd1;
rxd2 = DFFEAS(rxd2_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , , , , , );


--parity is parity at LC_X3_Y2_N6
--operation mode is normal

parity_lut_out = !parity;
parity = DFFEAS(parity_lut_out, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L37, , , , );


--A1L62 is always6~36 at LC_X3_Y2_N7
--operation mode is normal

A1L62 = no_bits_rcvd[3] $ (no_bits_rcvd[1] # no_bits_rcvd[0] # no_bits_rcvd[2]);


--A1L16 is framing_error~1 at LC_X3_Y2_N9
--operation mode is normal

A1L16 = !A1L62 & !parity & !A1L58;


--A1L17 is parity_error~1 at LC_X3_Y2_N0
--operation mode is normal

A1L17 = !A1L62 & parity & !A1L58;


--clkdiv[2] is clkdiv[2] at LC_X5_Y3_N4
--operation mode is normal

clkdiv[2]_lut_out = !clkdiv[2];
clkdiv[2] = DFFEAS(clkdiv[2]_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , A1L64, , , , );


--clkdiv[1] is clkdiv[1] at LC_X5_Y3_N2
--operation mode is normal

clkdiv[1]_lut_out = !clkdiv[1];
clkdiv[1] = DFFEAS(clkdiv[1]_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , A1L44, , , , );


--clk1x_enable is clk1x_enable at LC_X5_Y2_N6
--operation mode is normal

clk1x_enable_lut_out = rxd1 & (clk1x_enable & A1L92 # !rxd2) # !rxd1 & (clk1x_enable & A1L92);
clk1x_enable = DFFEAS(clk1x_enable_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , , , , , );


--clkdiv[0] is clkdiv[0] at LC_X6_Y3_N4
--operation mode is normal

clkdiv[0]_lut_out = !clkdiv[0];
clkdiv[0] = DFFEAS(clkdiv[0]_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , clk1x_enable, , , , );


--A1L84 is clkdiv[3]~40 at LC_X5_Y3_N8
--operation mode is normal

A1L84 = clkdiv[2] & clkdiv[0] & clk1x_enable & clkdiv[1];


--A1L86 is no_bits_rcvd~0 at LC_X6_Y2_N2
--operation mode is normal

A1L86 = rst # !clk1x_enable;


--A1L1 is add~265 at LC_X5_Y2_N4
--operation mode is normal

A1L1 = no_bits_rcvd[0] & no_bits_rcvd[1];


--A1L2 is add~266 at LC_X4_Y2_N8
--operation mode is normal

A1L2 = no_bits_rcvd[1] & no_bits_rcvd[2] & no_bits_rcvd[0];


--clk is clk at LC_X2_Y3_N7
--operation mode is normal

clk_lut_out = !clk;
clk = DFFEAS(clk_lut_out, clk50, VCC, , , , , , );


--clkdiv2[6] is clkdiv2[6] at LC_X2_Y1_N2
--operation mode is normal

clkdiv2[6]_lut_out = !A1L38 & (A1L4);
clkdiv2[6] = DFFEAS(clkdiv2[6]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , , , );


--A1L78 is reduce_nor~75 at LC_X2_Y1_N4
--operation mode is normal

clkdiv2[7]_qfbk = clkdiv2[7];
A1L78 = clkdiv2[7]_qfbk # !clkdiv2[6];

--clkdiv2[7] is clkdiv2[7] at LC_X2_Y1_N4
--operation mode is normal

clkdiv2[7] = DFFEAS(A1L78, GLOBAL(clk), !GLOBAL(rst), , , A1L3, , , VCC);


--clkdiv2[4] is clkdiv2[4] at LC_X2_Y1_N9
--operation mode is normal

clkdiv2[4]_lut_out = A1L01;
clkdiv2[4] = DFFEAS(clkdiv2[4]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , , , );


--clkdiv2[2] is clkdiv2[2] at LC_X3_Y1_N8
--operation mode is normal

clkdiv2[2]_lut_out = !A1L38 & A1L41;
clkdiv2[2] = DFFEAS(clkdiv2[2]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , , , );


--clkdiv2[3] is clkdiv2[3] at LC_X2_Y1_N6
--operation mode is normal

clkdiv2[3]_lut_out = A1L71 & !A1L38;
clkdiv2[3] = DFFEAS(clkdiv2[3]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , , , );


--clkdiv2[0] is clkdiv2[0] at LC_X4_Y1_N8
--operation mode is normal

clkdiv2[0]_lut_out = A1L32;
clkdiv2[0] = DFFEAS(clkdiv2[0]_lut_out, GLOBAL(clk), !GLOBAL(rst), , , , , , );


--A1L88 is reduce_nor~76 at LC_X3_Y1_N9
--operation mode is normal

clkdiv2[1]_qfbk = clkdiv2[1];
A1L88 = clkdiv2[2] # !clkdiv2[0] # !clkdiv2[1]_qfbk # !clkdiv2[3];

--clkdiv2[1] is clkdiv2[1] at LC_X3_Y1_N9
--operation mode is normal

clkdiv2[1] = DFFEAS(A1L88, GLOBAL(clk), !GLOBAL(rst), , , A1L02, , , VCC);


--A1L38 is reduce_nor~0 at LC_X2_Y1_N5
--operation mode is normal

clkdiv2[5]_qfbk = clkdiv2[5];
A1L38 = !clkdiv2[4] & !A1L88 & !clkdiv2[5]_qfbk & !A1L78;

--clkdiv2[5] is clkdiv2[5] at LC_X2_Y1_N5
--operation mode is normal

clkdiv2[5] = DFFEAS(A1L38, GLOBAL(clk), !GLOBAL(rst), , , A1L7, , , VCC);


--rxd1 is rxd1 at LC_X2_Y4_N5
--operation mode is normal

rxd1_lut_out = !rxd;
rxd1 = DFFEAS(rxd1_lut_out, GLOBAL(clk16x), !GLOBAL(rst), , , , , , );


--A1L37 is parity~0 at LC_X2_Y2_N8
--operation mode is normal

rsr[7]_qfbk = rsr[7];
A1L37 = rsr[7]_qfbk & A1L62;

--rsr[7] is rsr[7] at LC_X2_Y2_N8
--operation mode is normal

rsr[7] = DFFEAS(A1L37, GLOBAL(clkdiv[3]), !GLOBAL(rst), , A1L62, rsr[6], , , VCC);


--A1L64 is clkdiv[2]~41 at LC_X5_Y3_N5
--operation mode is normal

A1L64 = clkdiv[0] & clk1x_enable & clkdiv[1];


--A1L44 is clkdiv[1]~42 at LC_X5_Y3_N6
--operation mode is normal

A1L44 = clk1x_enable & clkdiv[0];


--A1L92 is clk1x_enable~46 at LC_X5_Y2_N5
--operation mode is normal

A1L92 = no_bits_rcvd[0] # no_bits_rcvd[1] # !no_bits_rcvd[2] # !no_bits_rcvd[3];


--A1L3 is add~267 at LC_X3_Y1_N7
--operation mode is normal

A1L3_carry_eqn = (!A1L11 & A1L5) # (A1L11 & A1L6);
A1L3 = A1L3_carry_eqn $ clkdiv2[7];


--A1L4 is add~272 at LC_X3_Y1_N6
--operation mode is arithmetic

A1L4_carry_eqn = (!A1L11 & A1L8) # (A1L11 & A1L9);
A1L4 = clkdiv2[6] $ !A1L4_carry_eqn;

--A1L5 is add~274 at LC_X3_Y1_N6
--operation mode is arithmetic

A1L5_cout_0 = clkdiv2[6] & !A1L8;
A1L5 = CARRY(A1L5_cout_0);

--A1L6 is add~274COUT1_323 at LC_X3_Y1_N6
--operation mode is arithmetic

A1L6_cout_1 = clkdiv2[6] & !A1L9;
A1L6 = CARRY(A1L6_cout_1);


--A1L7 is add~277 at LC_X3_Y1_N5
--operation mode is arithmetic

A1L7_carry_eqn = (!A1L11 & GND) # (A1L11 & VCC);
A1L7 = clkdiv2[5] $ (A1L7_carry_eqn);

--A1L8 is add~279 at LC_X3_Y1_N5
--operation mode is arithmetic

A1L8_cout_0 = !A1L11 # !clkdiv2[5];
A1L8 = CARRY(A1L8_cout_0);

--A1L9 is add~279COUT1_321 at LC_X3_Y1_N5
--operation mode is arithmetic

A1L9_cout_1 = !A1L11 # !clkdiv2[5];
A1L9 = CARRY(A1L9_cout_1);


--A1L01 is add~282 at LC_X3_Y1_N4
--operation mode is arithmetic

A1L01 = clkdiv2[4] $ (!A1L81);

--A1L11 is add~284 at LC_X3_Y1_N4
--operation mode is arithmetic

A1L11 = A1L21;


--A1L41 is add~287 at LC_X3_Y1_N2
--operation mode is arithmetic

A1L41 = clkdiv2[2] $ (!A1L12);

--A1L51 is add~289 at LC_X3_Y1_N2
--operation mode is arithmetic

A1L51_cout_0 = clkdiv2[2] & (!A1L12);
A1L51 = CARRY(A1L51_cout_0);

--A1L61 is add~289COUT1_318 at LC_X3_Y1_N2
--operation mode is arithmetic

A1L61_cout_1 = clkdiv2[2] & (!A1L22);
A1L61 = CARRY(A1L61_cout_1);


--A1L71 is add~292 at LC_X3_Y1_N3
--operation mode is arithmetic

A1L71 = clkdiv2[3] $ A1L51;

--A1L81 is add~294 at LC_X3_Y1_N3
--operation mode is arithmetic

A1L81_cout_0 = !A1L51 # !clkdiv2[3];
A1L81 = CARRY(A1L81_cout_0);

--A1L91 is add~294COUT1_319 at LC_X3_Y1_N3
--operation mode is arithmetic

A1L91_cout_1 = !A1L61 # !clkdiv2[3];
A1L91 = CARRY(A1L91_cout_1);


--A1L02 is add~297 at LC_X3_Y1_N1
--operation mode is arithmetic

A1L02 = clkdiv2[1] $ A1L42;

--A1L12 is add~299 at LC_X3_Y1_N1
--operation mode is arithmetic

A1L12_cout_0 = !A1L42 # !clkdiv2[1];
A1L12 = CARRY(A1L12_cout_0);

--A1L22 is add~299COUT1_316 at LC_X3_Y1_N1
--operation mode is arithmetic

A1L22_cout_1 = !A1L52 # !clkdiv2[1];
A1L22 = CARRY(A1L22_cout_1);


--A1L32 is add~302 at LC_X3_Y1_N0
--operation mode is arithmetic

A1L32 = !clkdiv2[0];

--A1L42 is add~304 at LC_X3_Y1_N0
--operation mode is arithmetic

A1L42_cout_0 = clkdiv2[0];
A1L42 = CARRY(A1L42_cout_0);

--A1L52 is add~304COUT1_314 at LC_X3_Y1_N0
--operation mode is arithmetic

A1L52_cout_1 = clkdiv2[0];
A1L52 = CARRY(A1L52_cout_1);


--rst is rst at PIN_78
--operation mode is input

rst = INPUT();


--clk50 is clk50 at PIN_12
--operation mode is input

clk50 = INPUT();


--rxd is rxd at PIN_3
--operation mode is input

rxd = INPUT();


--dout[0] is dout[0] at PIN_4
--operation mode is output

dout[0] = OUTPUT(rbr[0]);


--dout[1] is dout[1] at PIN_5
--operation mode is output

dout[1] = OUTPUT(rbr[1]);


--dout[2] is dout[2] at PIN_6
--operation mode is output

dout[2] = OUTPUT(rbr[2]);


--dout[3] is dout[3] at PIN_7
--operation mode is output

dout[3] = OUTPUT(rbr[3]);


--dout[4] is dout[4] at PIN_8
--operation mode is output

dout[4] = OUTPUT(rbr[4]);


--dout[5] is dout[5] at PIN_15
--operation mode is output

dout[5] = OUTPUT(rbr[5]);


--dout[6] is dout[6] at PIN_16
--operation mode is output

dout[6] = OUTPUT(rbr[6]);


--dout[7] is dout[7] at PIN_17
--operation mode is output

dout[7] = OUTPUT(rbr[7]);


--data_ready is data_ready at PIN_37
--operation mode is output

data_ready = OUTPUT(A1L05Q);


--framing_error is framing_error at PIN_14
--operation mode is output

framing_error = OUTPUT(A1L26Q);


--parity_error is parity_error at PIN_89
--operation mode is output

parity_error = OUTPUT(A1L27Q);