recuart.tan.qmsg

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序

{ "Info" "ITDB_TH_RESULT" "rxd1 rxd clk50 5.759 ns register " "Info: th for register \"rxd1\" (data pin = \"rxd\", clock pin = \"clk50\") is 5.759 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 destination 11.878 ns + Longest register " "Info: + Longest clock path from clock \"clk50\" to destination register is 11.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(1.294 ns) 3.635 ns clk 2 REG LC_X2_Y3_N4 10 " "Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { clk50 clk } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.675 ns clk16x 3 REG LC_X4_Y3_N4 9 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.040 ns" { clk clk16x } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.285 ns) + CELL(0.918 ns) 11.878 ns rxd1 4 REG LC_X3_Y3_N3 2 " "Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.203 ns" { clk16x rxd1 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.31 % ) " "Info: Total cell delay = 4.669 ns ( 39.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.209 ns ( 60.69 % ) " "Info: Total interconnect delay = 7.209 ns ( 60.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x rxd1 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.340 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rxd 1 PIN PIN_3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'rxd'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.617 ns) + CELL(0.591 ns) 6.340 ns rxd1 2 REG LC_X3_Y3_N3 2 " "Info: 2: + IC(4.617 ns) + CELL(0.591 ns) = 6.340 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.208 ns" { rxd rxd1 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 27.18 % ) " "Info: Total cell delay = 1.723 ns ( 27.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.617 ns ( 72.82 % ) " "Info: Total interconnect delay = 4.617 ns ( 72.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.340 ns" { rxd rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.340 ns" { rxd rxd~combout rxd1 } { 0.000ns 0.000ns 4.617ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x rxd1 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.340 ns" { rxd rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.340 ns" { rxd rxd~combout rxd1 } { 0.000ns 0.000ns 4.617ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 25 18:57:15 2007 " "Info: Processing ended: Sun Nov 25 18:57:15 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}