recuart.tan.qmsg

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk50 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"clk50\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "rxd2 framing_error~reg0 clk50 455 ps " "Info: Found hold time violation between source  pin or register \"rxd2\" and destination pin or register \"framing_error~reg0\" for clock \"clk50\" (Hold time is 455 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.038 ns + Largest " "Info: + Largest clock skew is 4.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 destination 15.916 ns + Longest register " "Info: + Longest clock path from clock \"clk50\" to destination register is 15.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(1.294 ns) 3.635 ns clk 2 REG LC_X2_Y3_N4 10 " "Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { clk50 clk } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.675 ns clk16x 3 REG LC_X4_Y3_N4 9 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.040 ns" { clk clk16x } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.285 ns) + CELL(1.294 ns) 12.254 ns clkdiv\[3\] 4 REG LC_X2_Y3_N8 24 " "Info: 4: + IC(3.285 ns) + CELL(1.294 ns) = 12.254 ns; Loc. = LC_X2_Y3_N8; Fanout = 24; REG Node = 'clkdiv\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.579 ns" { clk16x clkdiv[3] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.744 ns) + CELL(0.918 ns) 15.916 ns framing_error~reg0 5 REG LC_X4_Y1_N5 2 " "Info: 5: + IC(2.744 ns) + CELL(0.918 ns) = 15.916 ns; Loc. = LC_X4_Y1_N5; Fanout = 2; REG Node = 'framing_error~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.662 ns" { clkdiv[3] framing_error~reg0 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 37.47 % ) " "Info: Total cell delay = 5.963 ns ( 37.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.953 ns ( 62.53 % ) " "Info: Total interconnect delay = 9.953 ns ( 62.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] framing_error~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] framing_error~reg0 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 source 11.878 ns - Shortest register " "Info: - Shortest clock path from clock \"clk50\" to source register is 11.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(1.294 ns) 3.635 ns clk 2 REG LC_X2_Y3_N4 10 " "Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { clk50 clk } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.675 ns clk16x 3 REG LC_X4_Y3_N4 9 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.040 ns" { clk clk16x } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.285 ns) + CELL(0.918 ns) 11.878 ns rxd2 4 REG LC_X3_Y2_N1 3 " "Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y2_N1; Fanout = 3; REG Node = 'rxd2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.203 ns" { clk16x rxd2 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.31 % ) " "Info: Total cell delay = 4.669 ns ( 39.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.209 ns ( 60.69 % ) " "Info: Total interconnect delay = 7.209 ns ( 60.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x rxd2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x rxd2 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] framing_error~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] framing_error~reg0 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x rxd2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x rxd2 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.428 ns - Shortest register register " "Info: - Shortest register to register delay is 3.428 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd2 1 REG LC_X3_Y2_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N1; Fanout = 3; REG Node = 'rxd2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd2 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns framing_error~186 2 COMB LC_X3_Y2_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X3_Y2_N1; Fanout = 1; COMB Node = 'framing_error~186'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.595 ns" { rxd2 framing_error~186 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.772 ns) + CELL(1.061 ns) 3.428 ns framing_error~reg0 3 REG LC_X4_Y1_N5 2 " "Info: 3: + IC(1.772 ns) + CELL(1.061 ns) = 3.428 ns; Loc. = LC_X4_Y1_N5; Fanout = 2; REG Node = 'framing_error~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.833 ns" { framing_error~186 framing_error~reg0 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.656 ns ( 48.31 % ) " "Info: Total cell delay = 1.656 ns ( 48.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.772 ns ( 51.69 % ) " "Info: Total interconnect delay = 1.772 ns ( 51.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.428 ns" { rxd2 framing_error~186 framing_error~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.428 ns" { rxd2 framing_error~186 framing_error~reg0 } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.595ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 115 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] framing_error~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] framing_error~reg0 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x rxd2 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x rxd2 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.428 ns" { rxd2 framing_error~186 framing_error~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.428 ns" { rxd2 framing_error~186 framing_error~reg0 } { 0.000ns 0.000ns 1.772ns } { 0.000ns 0.595ns 1.061ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "rxd1 rxd clk50 -5.205 ns register " "Info: tsu for register \"rxd1\" (data pin = \"rxd\", clock pin = \"clk50\") is -5.205 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.340 ns + Longest pin register " "Info: + Longest pin to register delay is 6.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rxd 1 PIN PIN_3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'rxd'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.617 ns) + CELL(0.591 ns) 6.340 ns rxd1 2 REG LC_X3_Y3_N3 2 " "Info: 2: + IC(4.617 ns) + CELL(0.591 ns) = 6.340 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.208 ns" { rxd rxd1 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 27.18 % ) " "Info: Total cell delay = 1.723 ns ( 27.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.617 ns ( 72.82 % ) " "Info: Total interconnect delay = 4.617 ns ( 72.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.340 ns" { rxd rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.340 ns" { rxd rxd~combout rxd1 } { 0.000ns 0.000ns 4.617ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 destination 11.878 ns - Shortest register " "Info: - Shortest clock path from clock \"clk50\" to destination register is 11.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(1.294 ns) 3.635 ns clk 2 REG LC_X2_Y3_N4 10 " "Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { clk50 clk } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.675 ns clk16x 3 REG LC_X4_Y3_N4 9 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.040 ns" { clk clk16x } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.285 ns) + CELL(0.918 ns) 11.878 ns rxd1 4 REG LC_X3_Y3_N3 2 " "Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.203 ns" { clk16x rxd1 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.31 % ) " "Info: Total cell delay = 4.669 ns ( 39.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.209 ns ( 60.69 % ) " "Info: Total interconnect delay = 7.209 ns ( 60.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x rxd1 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.340 ns" { rxd rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.340 ns" { rxd rxd~combout rxd1 } { 0.000ns 0.000ns 4.617ns } { 0.000ns 1.132ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x rxd1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x rxd1 } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk50 dout\[2\] rbr\[2\] 20.531 ns register " "Info: tco from clock \"clk50\" to destination pin \"dout\[2\]\" through register \"rbr\[2\]\" is 20.531 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 source 15.916 ns + Longest register " "Info: + Longest clock path from clock \"clk50\" to source register is 15.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(1.294 ns) 3.635 ns clk 2 REG LC_X2_Y3_N4 10 " "Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { clk50 clk } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.675 ns clk16x 3 REG LC_X4_Y3_N4 9 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.040 ns" { clk clk16x } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.285 ns) + CELL(1.294 ns) 12.254 ns clkdiv\[3\] 4 REG LC_X2_Y3_N8 24 " "Info: 4: + IC(3.285 ns) + CELL(1.294 ns) = 12.254 ns; Loc. = LC_X2_Y3_N8; Fanout = 24; REG Node = 'clkdiv\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.579 ns" { clk16x clkdiv[3] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.744 ns) + CELL(0.918 ns) 15.916 ns rbr\[2\] 5 REG LC_X3_Y3_N4 1 " "Info: 5: + IC(2.744 ns) + CELL(0.918 ns) = 15.916 ns; Loc. = LC_X3_Y3_N4; Fanout = 1; REG Node = 'rbr\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.662 ns" { clkdiv[3] rbr[2] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 37.47 % ) " "Info: Total cell delay = 5.963 ns ( 37.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.953 ns ( 62.53 % ) " "Info: Total interconnect delay = 9.953 ns ( 62.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] rbr[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] rbr[2] } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 115 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.239 ns + Longest register pin " "Info: + Longest register to pin delay is 4.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rbr\[2\] 1 REG LC_X3_Y3_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y3_N4; Fanout = 1; REG Node = 'rbr\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rbr[2] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.917 ns) + CELL(2.322 ns) 4.239 ns dout\[2\] 2 PIN PIN_6 0 " "Info: 2: + IC(1.917 ns) + CELL(2.322 ns) = 4.239 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'dout\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.239 ns" { rbr[2] dout[2] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 54.78 % ) " "Info: Total cell delay = 2.322 ns ( 54.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.917 ns ( 45.22 % ) " "Info: Total interconnect delay = 1.917 ns ( 45.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.239 ns" { rbr[2] dout[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.239 ns" { rbr[2] dout[2] } { 0.000ns 1.917ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] rbr[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] rbr[2] } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.239 ns" { rbr[2] dout[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.239 ns" { rbr[2] dout[2] } { 0.000ns 1.917ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}