recuart.tan.qmsg

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk50 " "Info: Assuming node \"clk50\" is an undefined clock" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk " "Info: Detected ripple clock \"clk\" as buffer" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk16x " "Info: Detected ripple clock \"clk16x\" as buffer" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk16x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkdiv\[3\] " "Info: Detected ripple clock \"clkdiv\[3\]\" as buffer" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 27 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkdiv\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk50 register no_bits_rcvd\[0\] register clk1x_enable 131.61 MHz 7.598 ns Internal " "Info: Clock \"clk50\" has Internal fmax of 131.61 MHz between source register \"no_bits_rcvd\[0\]\" and destination register \"clk1x_enable\" (period= 7.598 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.851 ns + Longest register register " "Info: + Longest register to register delay is 2.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns no_bits_rcvd\[0\] 1 REG LC_X3_Y2_N6 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N6; Fanout = 10; REG Node = 'no_bits_rcvd\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { no_bits_rcvd[0] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.914 ns) 1.955 ns clk1x_enable~46 2 COMB LC_X3_Y2_N3 1 " "Info: 2: + IC(1.041 ns) + CELL(0.914 ns) = 1.955 ns; Loc. = LC_X3_Y2_N3; Fanout = 1; COMB Node = 'clk1x_enable~46'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.955 ns" { no_bits_rcvd[0] clk1x_enable~46 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 2.851 ns clk1x_enable 3 REG LC_X3_Y2_N4 6 " "Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.851 ns; Loc. = LC_X3_Y2_N4; Fanout = 6; REG Node = 'clk1x_enable'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.896 ns" { clk1x_enable~46 clk1x_enable } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.505 ns ( 52.79 % ) " "Info: Total cell delay = 1.505 ns ( 52.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.346 ns ( 47.21 % ) " "Info: Total interconnect delay = 1.346 ns ( 47.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.851 ns" { no_bits_rcvd[0] clk1x_enable~46 clk1x_enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.851 ns" { no_bits_rcvd[0] clk1x_enable~46 clk1x_enable } { 0.000ns 1.041ns 0.305ns } { 0.000ns 0.914ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.038 ns - Smallest " "Info: - Smallest clock skew is -4.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 destination 11.878 ns + Shortest register " "Info: + Shortest clock path from clock \"clk50\" to destination register is 11.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(1.294 ns) 3.635 ns clk 2 REG LC_X2_Y3_N4 10 " "Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { clk50 clk } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.675 ns clk16x 3 REG LC_X4_Y3_N4 9 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.040 ns" { clk clk16x } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.285 ns) + CELL(0.918 ns) 11.878 ns clk1x_enable 4 REG LC_X3_Y2_N4 6 " "Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y2_N4; Fanout = 6; REG Node = 'clk1x_enable'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.203 ns" { clk16x clk1x_enable } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.31 % ) " "Info: Total cell delay = 4.669 ns ( 39.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.209 ns ( 60.69 % ) " "Info: Total interconnect delay = 7.209 ns ( 60.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x clk1x_enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x clk1x_enable } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50 source 15.916 ns - Longest register " "Info: - Longest clock path from clock \"clk50\" to source register is 15.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk50 } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(1.294 ns) 3.635 ns clk 2 REG LC_X2_Y3_N4 10 " "Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { clk50 clk } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.675 ns clk16x 3 REG LC_X4_Y3_N4 9 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.040 ns" { clk clk16x } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.285 ns) + CELL(1.294 ns) 12.254 ns clkdiv\[3\] 4 REG LC_X2_Y3_N8 24 " "Info: 4: + IC(3.285 ns) + CELL(1.294 ns) = 12.254 ns; Loc. = LC_X2_Y3_N8; Fanout = 24; REG Node = 'clkdiv\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.579 ns" { clk16x clkdiv[3] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.744 ns) + CELL(0.918 ns) 15.916 ns no_bits_rcvd\[0\] 5 REG LC_X3_Y2_N6 10 " "Info: 5: + IC(2.744 ns) + CELL(0.918 ns) = 15.916 ns; Loc. = LC_X3_Y2_N6; Fanout = 10; REG Node = 'no_bits_rcvd\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.662 ns" { clkdiv[3] no_bits_rcvd[0] } "NODE_NAME" } } { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 37.47 % ) " "Info: Total cell delay = 5.963 ns ( 37.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.953 ns ( 62.53 % ) " "Info: Total interconnect delay = 9.953 ns ( 62.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] no_bits_rcvd[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] no_bits_rcvd[0] } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x clk1x_enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x clk1x_enable } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] no_bits_rcvd[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] no_bits_rcvd[0] } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 148 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "rcvr.v" "" { Text "F:/CPLD-FPGA/dboard V2/firmware/verilog/recuart_50m/rcvr.v" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.851 ns" { no_bits_rcvd[0] clk1x_enable~46 clk1x_enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.851 ns" { no_bits_rcvd[0] clk1x_enable~46 clk1x_enable } { 0.000ns 1.041ns 0.305ns } { 0.000ns 0.914ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.878 ns" { clk50 clk clk16x clk1x_enable } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "11.878 ns" { clk50 clk50~combout clk clk16x clk1x_enable } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.916 ns" { clk50 clk clk16x clkdiv[3] no_bits_rcvd[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.916 ns" { clk50 clk50~combout clk clk16x clkdiv[3] no_bits_rcvd[0] } { 0.000ns 0.000ns 1.178ns 2.746ns 3.285ns 2.744ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}