recuart.map.eqn

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序

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--rbr[0] is rbr[0]
--operation mode is normal

rbr[0]_lut_out = rsr[0];
rbr[0] = DFFEAS(rbr[0]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--rbr[1] is rbr[1]
--operation mode is normal

rbr[1]_lut_out = rsr[1];
rbr[1] = DFFEAS(rbr[1]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--rbr[2] is rbr[2]
--operation mode is normal

rbr[2]_lut_out = rsr[2];
rbr[2] = DFFEAS(rbr[2]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--rbr[3] is rbr[3]
--operation mode is normal

rbr[3]_lut_out = rsr[3];
rbr[3] = DFFEAS(rbr[3]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--rbr[4] is rbr[4]
--operation mode is normal

rbr[4]_lut_out = rsr[4];
rbr[4] = DFFEAS(rbr[4]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--rbr[5] is rbr[5]
--operation mode is normal

rbr[5]_lut_out = rsr[5];
rbr[5] = DFFEAS(rbr[5]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--rbr[6] is rbr[6]
--operation mode is normal

rbr[6]_lut_out = rsr[6];
rbr[6] = DFFEAS(rbr[6]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--rbr[7] is rbr[7]
--operation mode is normal

rbr[7]_lut_out = rsr[7];
rbr[7] = DFFEAS(rbr[7]_lut_out, clkdiv[3], !rst, , A1L77, , , , );


--A1L24Q is data_ready~reg0
--operation mode is normal

A1L24Q_lut_out = VCC;
A1L24Q = DFFEAS(A1L24Q_lut_out, clk16x, !rst, , A1L67, , , , );


--A1L45Q is framing_error~reg0
--operation mode is normal

A1L45Q_lut_out = !no_bits_rcvd[0] & (A1L87 & rxd2);
A1L45Q = DFFEAS(A1L45Q_lut_out, clkdiv[3], !rst, , A1L35, , , , );


--A1L46Q is parity_error~reg0
--operation mode is normal

A1L46Q_lut_out = VCC;
A1L46Q = DFFEAS(A1L46Q_lut_out, clkdiv[3], !rst, , A1L36, , , , );


--rsr[0] is rsr[0]
--operation mode is normal

rsr[0]_lut_out = !rxd2;
rsr[0] = DFFEAS(rsr[0]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--clkdiv[3] is clkdiv[3]
--operation mode is normal

clkdiv[3]_lut_out = !clkdiv[3];
clkdiv[3] = DFFEAS(clkdiv[3]_lut_out, clk16x, !rst, , A1L04, , , , );


--no_bits_rcvd[2] is no_bits_rcvd[2]
--operation mode is normal

no_bits_rcvd[2]_lut_out = !no_bits_rcvd[2];
no_bits_rcvd[2] = DFFEAS(no_bits_rcvd[2]_lut_out, clkdiv[3], !A1L06, , A1L1, , , , );


--no_bits_rcvd[1] is no_bits_rcvd[1]
--operation mode is normal

no_bits_rcvd[1]_lut_out = !no_bits_rcvd[1];
no_bits_rcvd[1] = DFFEAS(no_bits_rcvd[1]_lut_out, clkdiv[3], !A1L06, , no_bits_rcvd[0], , , , );


--no_bits_rcvd[0] is no_bits_rcvd[0]
--operation mode is normal

no_bits_rcvd[0]_lut_out = !no_bits_rcvd[0];
no_bits_rcvd[0] = DFFEAS(no_bits_rcvd[0]_lut_out, clkdiv[3], !A1L06, , , , , , );


--no_bits_rcvd[3] is no_bits_rcvd[3]
--operation mode is normal

no_bits_rcvd[3]_lut_out = !no_bits_rcvd[3];
no_bits_rcvd[3] = DFFEAS(no_bits_rcvd[3]_lut_out, clkdiv[3], !A1L06, , A1L2, , , , );


--A1L77 is reduce_nor~73
--operation mode is normal

A1L77 = !no_bits_rcvd[2] & !no_bits_rcvd[1] & no_bits_rcvd[0] & no_bits_rcvd[3];


--rsr[1] is rsr[1]
--operation mode is normal

rsr[1]_lut_out = rsr[0];
rsr[1] = DFFEAS(rsr[1]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--rsr[2] is rsr[2]
--operation mode is normal

rsr[2]_lut_out = rsr[1];
rsr[2] = DFFEAS(rsr[2]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--rsr[3] is rsr[3]
--operation mode is normal

rsr[3]_lut_out = rsr[2];
rsr[3] = DFFEAS(rsr[3]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--rsr[4] is rsr[4]
--operation mode is normal

rsr[4]_lut_out = rsr[3];
rsr[4] = DFFEAS(rsr[4]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--rsr[5] is rsr[5]
--operation mode is normal

rsr[5]_lut_out = rsr[4];
rsr[5] = DFFEAS(rsr[5]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--rsr[6] is rsr[6]
--operation mode is normal

rsr[6]_lut_out = rsr[5];
rsr[6] = DFFEAS(rsr[6]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--rsr[7] is rsr[7]
--operation mode is normal

rsr[7]_lut_out = rsr[6];
rsr[7] = DFFEAS(rsr[7]_lut_out, clkdiv[3], !rst, , A1L81, , , , );


--clk16x is clk16x
--operation mode is normal

clk16x_lut_out = !clk16x;
clk16x = DFFEAS(clk16x_lut_out, clk, !rst, , A1L57, , , , );


--A1L67 is reduce_nor~2
--operation mode is normal

A1L67 = !no_bits_rcvd[2] & no_bits_rcvd[1] & no_bits_rcvd[0] & no_bits_rcvd[3];


--A1L87 is reduce_nor~74
--operation mode is normal

A1L87 = no_bits_rcvd[1] & no_bits_rcvd[3] & (!no_bits_rcvd[2]);


--rxd2 is rxd2
--operation mode is normal

rxd2_lut_out = rxd1;
rxd2 = DFFEAS(rxd2_lut_out, clk16x, !rst, , , , , , );


--parity is parity
--operation mode is normal

parity_lut_out = !parity;
parity = DFFEAS(parity_lut_out, clkdiv[3], !rst, , A1L56, , , , );


--A1L81 is always6~36
--operation mode is normal

A1L81 = no_bits_rcvd[3] $ (no_bits_rcvd[2] # no_bits_rcvd[1] # no_bits_rcvd[0]);


--A1L35 is framing_error~1
--operation mode is normal

A1L35 = !A1L77 & (!parity & !A1L81);


--A1L36 is parity_error~1
--operation mode is normal

A1L36 = !A1L77 & parity & (!A1L81);


--clkdiv[2] is clkdiv[2]
--operation mode is normal

clkdiv[2]_lut_out = !clkdiv[2];
clkdiv[2] = DFFEAS(clkdiv[2]_lut_out, clk16x, !rst, , A1L83, , , , );


--clkdiv[1] is clkdiv[1]
--operation mode is normal

clkdiv[1]_lut_out = !clkdiv[1];
clkdiv[1] = DFFEAS(clkdiv[1]_lut_out, clk16x, !rst, , A1L63, , , , );


--clk1x_enable is clk1x_enable
--operation mode is normal

clk1x_enable_lut_out = clk1x_enable & (A1L12 # rxd1 & !rxd2) # !clk1x_enable & (rxd1 & !rxd2);
clk1x_enable = DFFEAS(clk1x_enable_lut_out, clk16x, !rst, , , , , , );


--clkdiv[0] is clkdiv[0]
--operation mode is normal

clkdiv[0]_lut_out = !clkdiv[0];
clkdiv[0] = DFFEAS(clkdiv[0]_lut_out, clk16x, !rst, , clk1x_enable, , , , );


--A1L04 is clkdiv[3]~40
--operation mode is normal

A1L04 = clkdiv[2] & clkdiv[1] & clk1x_enable & clkdiv[0];


--A1L06 is no_bits_rcvd~0
--operation mode is normal

A1L06 = rst # !clk1x_enable;


--A1L1 is add~265
--operation mode is normal

A1L1 = no_bits_rcvd[1] & no_bits_rcvd[0];


--A1L2 is add~266
--operation mode is normal

A1L2 = no_bits_rcvd[2] & no_bits_rcvd[1] & no_bits_rcvd[0];


--clk is clk
--operation mode is normal

clk_lut_out = !clk;
clk = DFFEAS(clk_lut_out, clk50, VCC, , , , , , );


--clkdiv2[7] is clkdiv2[7]
--operation mode is normal

clkdiv2[7]_lut_out = A1L3;
clkdiv2[7] = DFFEAS(clkdiv2[7]_lut_out, clk, !rst, , , , , , );


--clkdiv2[6] is clkdiv2[6]
--operation mode is normal

clkdiv2[6]_lut_out = A1L4 & !A1L57;
clkdiv2[6] = DFFEAS(clkdiv2[6]_lut_out, clk, !rst, , , , , , );


--A1L97 is reduce_nor~75
--operation mode is normal

A1L97 = clkdiv2[7] # !clkdiv2[6];


--clkdiv2[5] is clkdiv2[5]
--operation mode is normal

clkdiv2[5]_lut_out = A1L6;
clkdiv2[5] = DFFEAS(clkdiv2[5]_lut_out, clk, !rst, , , , , , );


--clkdiv2[4] is clkdiv2[4]
--operation mode is normal

clkdiv2[4]_lut_out = A1L8;
clkdiv2[4] = DFFEAS(clkdiv2[4]_lut_out, clk, !rst, , , , , , );


--clkdiv2[2] is clkdiv2[2]
--operation mode is normal

clkdiv2[2]_lut_out = A1L01 & !A1L57;
clkdiv2[2] = DFFEAS(clkdiv2[2]_lut_out, clk, !rst, , , , , , );


--clkdiv2[3] is clkdiv2[3]
--operation mode is normal

clkdiv2[3]_lut_out = A1L21 & !A1L57;
clkdiv2[3] = DFFEAS(clkdiv2[3]_lut_out, clk, !rst, , , , , , );


--clkdiv2[1] is clkdiv2[1]
--operation mode is normal

clkdiv2[1]_lut_out = A1L41;
clkdiv2[1] = DFFEAS(clkdiv2[1]_lut_out, clk, !rst, , , , , , );


--clkdiv2[0] is clkdiv2[0]
--operation mode is normal

clkdiv2[0]_lut_out = A1L61;
clkdiv2[0] = DFFEAS(clkdiv2[0]_lut_out, clk, !rst, , , , , , );


--A1L08 is reduce_nor~76
--operation mode is normal

A1L08 = clkdiv2[2] # !clkdiv2[0] # !clkdiv2[1] # !clkdiv2[3];


--A1L57 is reduce_nor~0
--operation mode is normal

A1L57 = !A1L97 & !clkdiv2[5] & !clkdiv2[4] & !A1L08;


--rxd1 is rxd1
--operation mode is normal

rxd1_lut_out = !rxd;
rxd1 = DFFEAS(rxd1_lut_out, clk16x, !rst, , , , , , );


--A1L56 is parity~0
--operation mode is normal

A1L56 = rsr[7] & A1L81;


--A1L83 is clkdiv[2]~41
--operation mode is normal

A1L83 = clkdiv[1] & clk1x_enable & clkdiv[0];


--A1L63 is clkdiv[1]~42
--operation mode is normal

A1L63 = clk1x_enable & clkdiv[0];


--A1L12 is clk1x_enable~46
--operation mode is normal

A1L12 = no_bits_rcvd[1] # no_bits_rcvd[0] # !no_bits_rcvd[3] # !no_bits_rcvd[2];


--A1L3 is add~267
--operation mode is normal

A1L3_carry_eqn = A1L5;
A1L3 = clkdiv2[7] $ (A1L3_carry_eqn);


--A1L4 is add~272
--operation mode is arithmetic

A1L4_carry_eqn = A1L7;
A1L4 = clkdiv2[6] $ (!A1L4_carry_eqn);

--A1L5 is add~274
--operation mode is arithmetic

A1L5 = CARRY(clkdiv2[6] & (!A1L7));


--A1L6 is add~277
--operation mode is arithmetic

A1L6_carry_eqn = A1L9;
A1L6 = clkdiv2[5] $ (A1L6_carry_eqn);

--A1L7 is add~279
--operation mode is arithmetic

A1L7 = CARRY(!A1L9 # !clkdiv2[5]);


--A1L8 is add~282
--operation mode is arithmetic

A1L8_carry_eqn = A1L31;
A1L8 = clkdiv2[4] $ (!A1L8_carry_eqn);

--A1L9 is add~284
--operation mode is arithmetic

A1L9 = CARRY(clkdiv2[4] & (!A1L31));


--A1L01 is add~287
--operation mode is arithmetic

A1L01_carry_eqn = A1L51;
A1L01 = clkdiv2[2] $ (!A1L01_carry_eqn);

--A1L11 is add~289
--operation mode is arithmetic

A1L11 = CARRY(clkdiv2[2] & (!A1L51));


--A1L21 is add~292
--operation mode is arithmetic

A1L21_carry_eqn = A1L11;
A1L21 = clkdiv2[3] $ (A1L21_carry_eqn);

--A1L31 is add~294
--operation mode is arithmetic

A1L31 = CARRY(!A1L11 # !clkdiv2[3]);


--A1L41 is add~297
--operation mode is arithmetic

A1L41_carry_eqn = A1L71;
A1L41 = clkdiv2[1] $ (A1L41_carry_eqn);

--A1L51 is add~299
--operation mode is arithmetic

A1L51 = CARRY(!A1L71 # !clkdiv2[1]);


--A1L61 is add~302
--operation mode is arithmetic

A1L61 = !clkdiv2[0];

--A1L71 is add~304
--operation mode is arithmetic

A1L71 = CARRY(clkdiv2[0]);


--rst is rst
--operation mode is input

rst = INPUT();


--clk50 is clk50
--operation mode is input

clk50 = INPUT();


--rxd is rxd
--operation mode is input

rxd = INPUT();


--dout[0] is dout[0]
--operation mode is output

dout[0] = OUTPUT(rbr[0]);


--dout[1] is dout[1]
--operation mode is output

dout[1] = OUTPUT(rbr[1]);


--dout[2] is dout[2]
--operation mode is output

dout[2] = OUTPUT(rbr[2]);


--dout[3] is dout[3]
--operation mode is output

dout[3] = OUTPUT(rbr[3]);


--dout[4] is dout[4]
--operation mode is output

dout[4] = OUTPUT(rbr[4]);


--dout[5] is dout[5]
--operation mode is output

dout[5] = OUTPUT(rbr[5]);


--dout[6] is dout[6]
--operation mode is output

dout[6] = OUTPUT(rbr[6]);


--dout[7] is dout[7]
--operation mode is output

dout[7] = OUTPUT(rbr[7]);


--data_ready is data_ready
--operation mode is output

data_ready = OUTPUT(A1L24Q);


--framing_error is framing_error
--operation mode is output

framing_error = OUTPUT(A1L45Q);


--parity_error is parity_error
--operation mode is output

parity_error = OUTPUT(A1L46Q);