recuart.tan.rpt

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序

            Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y2_N4; Fanout = 6; REG Node = 'clk1x_enable'
            Info: Total cell delay = 4.669 ns ( 39.31 % )
            Info: Total interconnect delay = 7.209 ns ( 60.69 % )
        Info: - Longest clock path from clock "clk50" to source register is 15.916 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
            Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'
            Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'
            Info: 4: + IC(3.285 ns) + CELL(1.294 ns) = 12.254 ns; Loc. = LC_X2_Y3_N8; Fanout = 24; REG Node = 'clkdiv[3]'
            Info: 5: + IC(2.744 ns) + CELL(0.918 ns) = 15.916 ns; Loc. = LC_X3_Y2_N6; Fanout = 10; REG Node = 'no_bits_rcvd[0]'
            Info: Total cell delay = 5.963 ns ( 37.47 % )
            Info: Total interconnect delay = 9.953 ns ( 62.53 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "clk50" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "rxd2" and destination pin or register "framing_error~reg0" for clock "clk50" (Hold time is 455 ps)
    Info: + Largest clock skew is 4.038 ns
        Info: + Longest clock path from clock "clk50" to destination register is 15.916 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
            Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'
            Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'
            Info: 4: + IC(3.285 ns) + CELL(1.294 ns) = 12.254 ns; Loc. = LC_X2_Y3_N8; Fanout = 24; REG Node = 'clkdiv[3]'
            Info: 5: + IC(2.744 ns) + CELL(0.918 ns) = 15.916 ns; Loc. = LC_X4_Y1_N5; Fanout = 2; REG Node = 'framing_error~reg0'
            Info: Total cell delay = 5.963 ns ( 37.47 % )
            Info: Total interconnect delay = 9.953 ns ( 62.53 % )
        Info: - Shortest clock path from clock "clk50" to source register is 11.878 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
            Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'
            Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'
            Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y2_N1; Fanout = 3; REG Node = 'rxd2'
            Info: Total cell delay = 4.669 ns ( 39.31 % )
            Info: Total interconnect delay = 7.209 ns ( 60.69 % )
    Info: - Micro clock to output delay of source is 0.376 ns
    Info: - Shortest register to register delay is 3.428 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N1; Fanout = 3; REG Node = 'rxd2'
        Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X3_Y2_N1; Fanout = 1; COMB Node = 'framing_error~186'
        Info: 3: + IC(1.772 ns) + CELL(1.061 ns) = 3.428 ns; Loc. = LC_X4_Y1_N5; Fanout = 2; REG Node = 'framing_error~reg0'
        Info: Total cell delay = 1.656 ns ( 48.31 % )
        Info: Total interconnect delay = 1.772 ns ( 51.69 % )
    Info: + Micro hold delay of destination is 0.221 ns
Info: tsu for register "rxd1" (data pin = "rxd", clock pin = "clk50") is -5.205 ns
    Info: + Longest pin to register delay is 6.340 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'rxd'
        Info: 2: + IC(4.617 ns) + CELL(0.591 ns) = 6.340 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'
        Info: Total cell delay = 1.723 ns ( 27.18 % )
        Info: Total interconnect delay = 4.617 ns ( 72.82 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk50" to destination register is 11.878 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
        Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'
        Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'
        Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'
        Info: Total cell delay = 4.669 ns ( 39.31 % )
        Info: Total interconnect delay = 7.209 ns ( 60.69 % )
Info: tco from clock "clk50" to destination pin "dout[2]" through register "rbr[2]" is 20.531 ns
    Info: + Longest clock path from clock "clk50" to source register is 15.916 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
        Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'
        Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'
        Info: 4: + IC(3.285 ns) + CELL(1.294 ns) = 12.254 ns; Loc. = LC_X2_Y3_N8; Fanout = 24; REG Node = 'clkdiv[3]'
        Info: 5: + IC(2.744 ns) + CELL(0.918 ns) = 15.916 ns; Loc. = LC_X3_Y3_N4; Fanout = 1; REG Node = 'rbr[2]'
        Info: Total cell delay = 5.963 ns ( 37.47 % )
        Info: Total interconnect delay = 9.953 ns ( 62.53 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.239 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y3_N4; Fanout = 1; REG Node = 'rbr[2]'
        Info: 2: + IC(1.917 ns) + CELL(2.322 ns) = 4.239 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'dout[2]'
        Info: Total cell delay = 2.322 ns ( 54.78 % )
        Info: Total interconnect delay = 1.917 ns ( 45.22 % )
Info: th for register "rxd1" (data pin = "rxd", clock pin = "clk50") is 5.759 ns
    Info: + Longest clock path from clock "clk50" to destination register is 11.878 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
        Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'
        Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'
        Info: 4: + IC(3.285 ns) + CELL(0.918 ns) = 11.878 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'
        Info: Total cell delay = 4.669 ns ( 39.31 % )
        Info: Total interconnect delay = 7.209 ns ( 60.69 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 6.340 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'rxd'
        Info: 2: + IC(4.617 ns) + CELL(0.591 ns) = 6.340 ns; Loc. = LC_X3_Y3_N3; Fanout = 2; REG Node = 'rxd1'
        Info: Total cell delay = 1.723 ns ( 27.18 % )
        Info: Total interconnect delay = 4.617 ns ( 72.82 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Sun Nov 25 18:57:15 2007
    Info: Elapsed time: 00:00:01