recuart.tan.rpt

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序

; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; framing_error~reg0 ; framing_error~reg0 ; clk50      ; clk50    ; None                        ; None                      ; 1.743 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; no_bits_rcvd[3]    ; no_bits_rcvd[3]    ; clk50      ; clk50    ; None                        ; None                      ; 1.550 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; clkdiv[1]          ; clkdiv[2]          ; clk50      ; clk50    ; None                        ; None                      ; 1.532 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; clkdiv[1]          ; clkdiv[1]          ; clk50      ; clk50    ; None                        ; None                      ; 1.520 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rsr[4]             ; rsr[5]             ; clk50      ; clk50    ; None                        ; None                      ; 1.501 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rsr[5]             ; rbr[5]             ; clk50      ; clk50    ; None                        ; None                      ; 1.256 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rsr[6]             ; rbr[6]             ; clk50      ; clk50    ; None                        ; None                      ; 1.255 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rsr[6]             ; rsr[7]             ; clk50      ; clk50    ; None                        ; None                      ; 1.250 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rsr[5]             ; rsr[6]             ; clk50      ; clk50    ; None                        ; None                      ; 1.249 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rsr[3]             ; rsr[4]             ; clk50      ; clk50    ; None                        ; None                      ; 1.247 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rsr[0]             ; rsr[1]             ; clk50      ; clk50    ; None                        ; None                      ; 1.221 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rxd2               ; rsr[0]             ; clk50      ; clk50    ; None                        ; None                      ; 3.488 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; rxd2               ; framing_error~reg0 ; clk50      ; clk50    ; None                        ; None                      ; 3.428 ns                ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk50'                                                                                                                                                               ;
+------------------------------------------+------+--------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From ; To                 ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+------+--------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; rxd2 ; framing_error~reg0 ; clk50      ; clk50    ; None                       ; None                       ; 3.428 ns                 ;
; Not operational: Clock Skew > Data Delay ; rxd2 ; rsr[0]             ; clk50      ; clk50    ; None                       ; None                       ; 3.488 ns                 ;
+------------------------------------------+------+--------------------+------------+----------+----------------------------+----------------------------+--------------------------+


+------------------------------------------------------------+
; tsu                                                        ;
+-------+--------------+------------+------+------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To   ; To Clock ;
+-------+--------------+------------+------+------+----------+
; N/A   ; None         ; -5.205 ns  ; rxd  ; rxd1 ; clk50    ;
+-------+--------------+------------+------+------+----------+


+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+--------------------+---------------+------------+
; Slack ; Required tco ; Actual tco ; From               ; To            ; From Clock ;
+-------+--------------+------------+--------------------+---------------+------------+
; N/A   ; None         ; 20.531 ns  ; rbr[2]             ; dout[2]       ; clk50      ;
; N/A   ; None         ; 20.519 ns  ; rbr[4]             ; dout[4]       ; clk50      ;
; N/A   ; None         ; 20.516 ns  ; rbr[3]             ; dout[3]       ; clk50      ;
; N/A   ; None         ; 19.426 ns  ; rbr[5]             ; dout[5]       ; clk50      ;
; N/A   ; None         ; 19.422 ns  ; rbr[7]             ; dout[7]       ; clk50      ;
; N/A   ; None         ; 19.422 ns  ; rbr[6]             ; dout[6]       ; clk50      ;
; N/A   ; None         ; 19.422 ns  ; rbr[1]             ; dout[1]       ; clk50      ;
; N/A   ; None         ; 19.422 ns  ; rbr[0]             ; dout[0]       ; clk50      ;
; N/A   ; None         ; 19.388 ns  ; framing_error~reg0 ; framing_error ; clk50      ;
; N/A   ; None         ; 19.382 ns  ; parity_error~reg0  ; parity_error  ; clk50      ;
; N/A   ; None         ; 16.639 ns  ; data_ready~reg0    ; data_ready    ; clk50      ;
+-------+--------------+------------+--------------------+---------------+------------+


+------------------------------------------------------------------+
; th                                                               ;
+---------------+-------------+-----------+------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To   ; To Clock ;
+---------------+-------------+-----------+------+------+----------+
; N/A           ; None        ; 5.759 ns  ; rxd  ; rxd1 ; clk50    ;
+---------------+-------------+-----------+------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Nov 25 18:57:14 2007
Info: Command: quartus_tan --lower_priority --read_settings_files=off --write_settings_files=off recuart -c recuart
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk50" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk" as buffer
    Info: Detected ripple clock "clk16x" as buffer
    Info: Detected ripple clock "clkdiv[3]" as buffer
Info: Clock "clk50" has Internal fmax of 131.61 MHz between source register "no_bits_rcvd[0]" and destination register "clk1x_enable" (period= 7.598 ns)
    Info: + Longest register to register delay is 2.851 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N6; Fanout = 10; REG Node = 'no_bits_rcvd[0]'
        Info: 2: + IC(1.041 ns) + CELL(0.914 ns) = 1.955 ns; Loc. = LC_X3_Y2_N3; Fanout = 1; COMB Node = 'clk1x_enable~46'
        Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.851 ns; Loc. = LC_X3_Y2_N4; Fanout = 6; REG Node = 'clk1x_enable'
        Info: Total cell delay = 1.505 ns ( 52.79 % )
        Info: Total interconnect delay = 1.346 ns ( 47.21 % )
    Info: - Smallest clock skew is -4.038 ns
        Info: + Shortest clock path from clock "clk50" to destination register is 11.878 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'clk50'
            Info: 2: + IC(1.178 ns) + CELL(1.294 ns) = 3.635 ns; Loc. = LC_X2_Y3_N4; Fanout = 10; REG Node = 'clk'
            Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.675 ns; Loc. = LC_X4_Y3_N4; Fanout = 9; REG Node = 'clk16x'