txxclock.tan.rpt

VHDL编写的数字钟

; Clock Hold: 'lHZCLK'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; hour:inst2|lpm_counter:sec2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; hour:inst2|lpm_counter:sec2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; lHZCLK     ; lHZCLK   ; 21           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                       ;                                                                       ;            ;          ; 111          ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1K30TC144-3      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; lHZCLK          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; modekey         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'lHZCLK'                                                                                                                                                                                                                                                                                              ;
+-------+------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                  ; To                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------------------+-----------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 41.49 MHz ( period = 24.100 ns )               ; hour:inst2|sec1[2]                                                    ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 41.49 MHz ( period = 24.100 ns )               ; hour:inst2|lpm_counter:sec2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 5.700 ns                ;
; N/A   ; 41.67 MHz ( period = 24.000 ns )               ; hour:inst2|lpm_counter:sec2_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 5.600 ns                ;
; N/A   ; 42.74 MHz ( period = 23.400 ns )               ; hour:inst2|sec1[3]                                                    ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 5.000 ns                ;
; N/A   ; 43.10 MHz ( period = 23.200 ns )               ; hour:inst2|lpm_counter:sec2_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 4.800 ns                ;
; N/A   ; 43.29 MHz ( period = 23.100 ns )               ; hour:inst2|lpm_counter:sec2_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 4.700 ns                ;
; N/A   ; 43.48 MHz ( period = 23.000 ns )               ; hour:inst2|sec1[1]                                                    ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 4.600 ns                ;
; N/A   ; 44.25 MHz ( period = 22.600 ns )               ; hour:inst2|sec1[0]                                                    ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 4.200 ns                ;
; N/A   ; 65.36 MHz ( period = 15.300 ns )               ; minute:inst1|sec1[2]                                                  ; cmp32B:inst7|y                                                        ; lHZCLK     ; lHZCLK   ; None                        ; None                      ; 5.800 ns                ;