txxclock.tan.qmsg

VHDL编写的数字钟

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "lHZCLK " "Info: Assuming node \"lHZCLK\" is an undefined clock" {  } { { "txxclock.bdf" "" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 256 -160 8 272 "lHZCLK" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "lHZCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "modekey " "Info: Assuming node \"modekey\" is an undefined clock" {  } { { "txxclock.bdf" "" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 416 -288 -120 432 "modekey" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "modekey" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "19 " "Warning: Found 19 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "selector12:inst10\|y " "Info: Detected ripple clock \"selector12:inst10\|y\" as buffer" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 15 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "selector12:inst10\|y" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "selector12:inst10\|x " "Info: Detected ripple clock \"selector12:inst10\|x\" as buffer" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 14 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "selector12:inst10\|x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "selector12:inst12\|y " "Info: Detected ripple clock \"selector12:inst12\|y\" as buffer" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 15 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "selector12:inst12\|y" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "selector12:inst12\|x " "Info: Detected ripple clock \"selector12:inst12\|x\" as buffer" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 14 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "selector12:inst12\|x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "minute:inst1\|sec1\[0\] " "Info: Detected ripple clock \"minute:inst1\|sec1\[0\]\" as buffer" {  } { { "minute.vhd" "" { Text "E:/study/EDA/myclock/txxclock/minute.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "minute:inst1\|sec1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "minute:inst1\|sec1\[1\] " "Info: Detected ripple clock \"minute:inst1\|sec1\[1\]\" as buffer" {  } { { "minute.vhd" "" { Text "E:/study/EDA/myclock/txxclock/minute.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "minute:inst1\|sec1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "minute:inst1\|sec1\[2\] " "Info: Detected ripple clock \"minute:inst1\|sec1\[2\]\" as buffer" {  } { { "minute.vhd" "" { Text "E:/study/EDA/myclock/txxclock/minute.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "minute:inst1\|sec1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "selector:inst5\|y~37 " "Info: Detected gated clock \"selector:inst5\|y~37\" as buffer" {  } { { "selector.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector.vhd" 3 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "selector:inst5\|y~37" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "minute:inst1\|sec1\[3\] " "Info: Detected ripple clock \"minute:inst1\|sec1\[3\]\" as buffer" {  } { { "minute.vhd" "" { Text "E:/study/EDA/myclock/txxclock/minute.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "minute:inst1\|sec1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "mode:inst9\|Equal2~10 " "Info: Detected gated clock \"mode:inst9\|Equal2~10\" as buffer" {  } { { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mode:inst9\|Equal2~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "minute:inst1\|s1~29 " "Info: Detected gated clock \"minute:inst1\|s1~29\" as buffer" {  } { { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "minute:inst1\|s1~29" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mode:inst9\|CQI\[0\] " "Info: Detected ripple clock \"mode:inst9\|CQI\[0\]\" as buffer" {  } { { "mode.vhd" "" { Text "E:/study/EDA/myclock/txxclock/mode.vhd" 21 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mode:inst9\|CQI\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "mode:inst9\|CQI\[1\] " "Info: Detected ripple clock \"mode:inst9\|CQI\[1\]\" as buffer" {  } { { "mode.vhd" "" { Text "E:/study/EDA/myclock/txxclock/mode.vhd" 21 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "mode:inst9\|CQI\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "selector:inst8\|y~37 " "Info: Detected gated clock \"selector:inst8\|y~37\" as buffer" {  } { { "selector.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector.vhd" 3 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "selector:inst8\|y~37" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second:inst\|sec1\[0\] " "Info: Detected ripple clock \"second:inst\|sec1\[0\]\" as buffer" {  } { { "second.vhd" "" { Text "E:/study/EDA/myclock/txxclock/second.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "second:inst\|sec1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second:inst\|sec1\[1\] " "Info: Detected ripple clock \"second:inst\|sec1\[1\]\" as buffer" {  } { { "second.vhd" "" { Text "E:/study/EDA/myclock/txxclock/second.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "second:inst\|sec1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "second:inst\|s1~29 " "Info: Detected gated clock \"second:inst\|s1~29\" as buffer" {  } { { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "second:inst\|s1~29" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second:inst\|sec1\[2\] " "Info: Detected ripple clock \"second:inst\|sec1\[2\]\" as buffer" {  } { { "second.vhd" "" { Text "E:/study/EDA/myclock/txxclock/second.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "second:inst\|sec1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second:inst\|sec1\[3\] " "Info: Detected ripple clock \"second:inst\|sec1\[3\]\" as buffer" {  } { { "second.vhd" "" { Text "E:/study/EDA/myclock/txxclock/second.vhd" 27 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "second:inst\|sec1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "lHZCLK register hour:inst2\|sec1\[2\] register cmp32B:inst7\|y 41.49 MHz 24.1 ns Internal " "Info: Clock \"lHZCLK\" has Internal fmax of 41.49 MHz between source register \"hour:inst2\|sec1\[2\]\" and destination register \"cmp32B:inst7\|y\" (period= 24.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.700 ns + Longest register register " "Info: + Longest register to register delay is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:inst2\|sec1\[2\] 1 REG LC2_F3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_F3; Fanout = 5; REG Node = 'hour:inst2\|sec1\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hour:inst2|sec1[2] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/study/EDA/myclock/txxclock/hour.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.100 ns) 2.100 ns cmp32B:inst7\|Equal0~194 2 COMB LC3_F2 1 " "Info: 2: + IC(1.000 ns) + CELL(1.100 ns) = 2.100 ns; Loc. = LC3_F2; Fanout = 1; COMB Node = 'cmp32B:inst7\|Equal0~194'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { hour:inst2|sec1[2] cmp32B:inst7|Equal0~194 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 3.700 ns cmp32B:inst7\|Equal0~179 3 COMB LC4_F2 1 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 3.700 ns; Loc. = LC4_F2; Fanout = 1; COMB Node = 'cmp32B:inst7\|Equal0~179'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { cmp32B:inst7|Equal0~194 cmp32B:inst7|Equal0~179 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.100 ns) 5.700 ns cmp32B:inst7\|y 4 REG LC5_F1 1 " "Info: 4: + IC(0.900 ns) + CELL(1.100 ns) = 5.700 ns; Loc. = LC5_F1; Fanout = 1; REG Node = 'cmp32B:inst7\|y'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { cmp32B:inst7|Equal0~179 cmp32B:inst7|y } "NODE_NAME" } } { "cmp32B.vhd" "" { Text "E:/study/EDA/myclock/txxclock/cmp32B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 66.67 % ) " "Info: Total cell delay = 3.800 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 33.33 % ) " "Info: Total interconnect delay = 1.900 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { hour:inst2|sec1[2] cmp32B:inst7|Equal0~194 cmp32B:inst7|Equal0~179 cmp32B:inst7|y } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { hour:inst2|sec1[2] cmp32B:inst7|Equal0~194 cmp32B:inst7|Equal0~179 cmp32B:inst7|y } { 0.000ns 1.000ns 0.000ns 0.900ns } { 0.000ns 1.100ns 1.600ns 1.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-17.300 ns - Smallest " "Info: - Smallest clock skew is -17.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lHZCLK destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"lHZCLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns lHZCLK 1 CLK PIN_55 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 9; CLK Node = 'lHZCLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lHZCLK } "NODE_NAME" } } { "txxclock.bdf" "" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 256 -160 8 272 "lHZCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cmp32B:inst7\|y 2 REG LC5_F1 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_F1; Fanout = 1; REG Node = 'cmp32B:inst7\|y'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { lHZCLK cmp32B:inst7|y } "NODE_NAME" } } { "cmp32B.vhd" "" { Text "E:/study/EDA/myclock/txxclock/cmp32B.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { lHZCLK cmp32B:inst7|y } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { lHZCLK lHZCLK~out cmp32B:inst7|y } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lHZCLK source 19.700 ns - Longest register " "Info: - Longest clock path from clock \"lHZCLK\" to source register is 19.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns lHZCLK 1 CLK PIN_55 9 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 9; CLK Node = 'lHZCLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lHZCLK } "NODE_NAME" } } { "txxclock.bdf" "" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 256 -160 8 272 "lHZCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns second:inst\|sec1\[3\] 2 REG LC1_B6 3 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_B6; Fanout = 3; REG Node = 'second:inst\|sec1\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { lHZCLK second:inst|sec1[3] } "NODE_NAME" } } { "second.vhd" "" { Text "E:/study/EDA/myclock/txxclock/second.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 5.500 ns second:inst\|s1~29 3 COMB LC1_B2 3 " "Info: 3: + IC(1.000 ns) + CELL(1.600 ns) = 5.500 ns; Loc. = LC1_B2; Fanout = 3; COMB Node = 'second:inst\|s1~29'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { second:inst|sec1[3] second:inst|s1~29 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.400 ns) 9.200 ns selector:inst5\|y~37 4 COMB LC4_F6 8 " "Info: 4: + IC(2.300 ns) + CELL(1.400 ns) = 9.200 ns; Loc. = LC4_F6; Fanout = 8; COMB Node = 'selector:inst5\|y~37'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { second:inst|s1~29 selector:inst5|y~37 } "NODE_NAME" } } { "selector.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector.vhd" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.500 ns) 11.300 ns minute:inst1\|sec1\[1\] 5 REG LC2_F11 5 " "Info: 5: + IC(1.600 ns) + CELL(0.500 ns) = 11.300 ns; Loc. = LC2_F11; Fanout = 5; REG Node = 'minute:inst1\|sec1\[1\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { selector:inst5|y~37 minute:inst1|sec1[1] } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/study/EDA/myclock/txxclock/minute.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 13.300 ns minute:inst1\|s1~29 6 COMB LC4_F11 3 " "Info: 6: + IC(0.300 ns) + CELL(1.700 ns) = 13.300 ns; Loc. = LC4_F11; Fanout = 3; COMB Node = 'minute:inst1\|s1~29'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { minute:inst1|sec1[1] minute:inst1|s1~29 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.400 ns) 16.000 ns selector:inst8\|y~37 7 COMB LC1_F8 9 " "Info: 7: + IC(1.300 ns) + CELL(1.400 ns) = 16.000 ns; Loc. = LC1_F8; Fanout = 9; COMB Node = 'selector:inst8\|y~37'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { minute:inst1|s1~29 selector:inst8|y~37 } "NODE_NAME" } } { "selector.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector.vhd" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(0.000 ns) 19.700 ns hour:inst2\|sec1\[2\] 8 REG LC2_F3 5 " "Info: 8: + IC(3.700 ns) + CELL(0.000 ns) = 19.700 ns; Loc. = LC2_F3; Fanout = 5; REG Node = 'hour:inst2\|sec1\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { selector:inst8|y~37 hour:inst2|sec1[2] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/study/EDA/myclock/txxclock/hour.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.100 ns ( 46.19 % ) " "Info: Total cell delay = 9.100 ns ( 46.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.600 ns ( 53.81 % ) " "Info: Total interconnect delay = 10.600 ns ( 53.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.700 ns" { lHZCLK second:inst|sec1[3] second:inst|s1~29 selector:inst5|y~37 minute:inst1|sec1[1] minute:inst1|s1~29 selector:inst8|y~37 hour:inst2|sec1[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "19.700 ns" { lHZCLK lHZCLK~out second:inst|sec1[3] second:inst|s1~29 selector:inst5|y~37 minute:inst1|sec1[1] minute:inst1|s1~29 selector:inst8|y~37 hour:inst2|sec1[2] } { 0.000ns 0.000ns 0.400ns 1.000ns 2.300ns 1.600ns 0.300ns 1.300ns 3.700ns } { 0.000ns 2.000ns 0.500ns 1.600ns 1.400ns 0.500ns 1.700ns 1.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { lHZCLK cmp32B:inst7|y } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { lHZCLK lHZCLK~out cmp32B:inst7|y } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.700 ns" { lHZCLK second:inst|sec1[3] second:inst|s1~29 selector:inst5|y~37 minute:inst1|sec1[1] minute:inst1|s1~29 selector:inst8|y~37 hour:inst2|sec1[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "19.700 ns" { lHZCLK lHZCLK~out second:inst|sec1[3] second:inst|s1~29 selector:inst5|y~37 minute:inst1|sec1[1] minute:inst1|s1~29 selector:inst8|y~37 hour:inst2|sec1[2] } { 0.000ns 0.000ns 0.400ns 1.000ns 2.300ns 1.600ns 0.300ns 1.300ns 3.700ns } { 0.000ns 2.000ns 0.500ns 1.600ns 1.400ns 0.500ns 1.700ns 1.400ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "hour.vhd" "" { Text "E:/study/EDA/myclock/txxclock/hour.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "cmp32B.vhd" "" { Text "E:/study/EDA/myclock/txxclock/cmp32B.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.700 ns" { hour:inst2|sec1[2] cmp32B:inst7|Equal0~194 cmp32B:inst7|Equal0~179 cmp32B:inst7|y } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.700 ns" { hour:inst2|sec1[2] cmp32B:inst7|Equal0~194 cmp32B:inst7|Equal0~179 cmp32B:inst7|y } { 0.000ns 1.000ns 0.000ns 0.900ns } { 0.000ns 1.100ns 1.600ns 1.100ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { lHZCLK cmp32B:inst7|y } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { lHZCLK lHZCLK~out cmp32B:inst7|y } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "19.700 ns" { lHZCLK second:inst|sec1[3] second:inst|s1~29 selector:inst5|y~37 minute:inst1|sec1[1] minute:inst1|s1~29 selector:inst8|y~37 hour:inst2|sec1[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "19.700 ns" { lHZCLK lHZCLK~out second:inst|sec1[3] second:inst|s1~29 selector:inst5|y~37 minute:inst1|sec1[1] minute:inst1|s1~29 selector:inst8|y~37 hour:inst2|sec1[2] } { 0.000ns 0.000ns 0.400ns 1.000ns 2.300ns 1.600ns 0.300ns 1.300ns 3.700ns } { 0.000ns 2.000ns 0.500ns 1.600ns 1.400ns 0.500ns 1.700ns 1.400ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}