txxclock.vhd

VHDL编写的数字钟

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY txxclock IS 
	port
	(
		modekey :  IN  STD_LOGIC;
		keyhour :  IN  STD_LOGIC;
		keyminute :  IN  STD_LOGIC;
		clkclock :  IN  STD_LOGIC;
		lHZCLK :  IN  STD_LOGIC;
		clockout :  OUT  STD_LOGIC;
		secondlow :  OUT  STD_LOGIC_VECTOR(3 downto 0);
		seconhigh :  OUT  STD_LOGIC_VECTOR(3 downto 0);
		timeout :  OUT  STD_LOGIC_VECTOR(15 downto 0)
	);
END txxclock;

ARCHITECTURE bdf_type OF txxclock IS 

component second
	PORT(clk : IN STD_LOGIC;
		 s_overflow : OUT STD_LOGIC;
		 s_dsph : OUT STD_LOGIC_VECTOR(3 downto 0);
		 s_dspl : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component minute
	PORT(clk : IN STD_LOGIC;
		 m_overflow : OUT STD_LOGIC;
		 m_dsph : OUT STD_LOGIC_VECTOR(3 downto 0);
		 m_dspl : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component selector12
	PORT(s : IN STD_LOGIC;
		 a : IN STD_LOGIC;
		 x : OUT STD_LOGIC;
		 y : OUT STD_LOGIC
	);
end component;

component selector
	PORT(a : IN STD_LOGIC;
		 b : IN STD_LOGIC;
		 s : IN STD_LOGIC;
		 y : OUT STD_LOGIC
	);
end component;

component hour
	PORT(clk : IN STD_LOGIC;
		 h_overflow : OUT STD_LOGIC;
		 h_dsph : OUT STD_LOGIC_VECTOR(3 downto 0);
		 h_dspl : OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component selector217
	PORT(s : IN STD_LOGIC;
		 a : IN STD_LOGIC_VECTOR(15 downto 0);
		 b : IN STD_LOGIC_VECTOR(15 downto 0);
		 y : OUT STD_LOGIC_VECTOR(15 downto 0)
	);
end component;

component cmp32b
	PORT(clk : IN STD_LOGIC;
		 A : IN STD_LOGIC_VECTOR(15 downto 0);
		 B : IN STD_LOGIC_VECTOR(15 downto 0);
		 y : OUT STD_LOGIC
	);
end component;

component mode
	PORT(modekey : IN STD_LOGIC;
		 OUTY : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

signal	clk :  STD_LOGIC;
signal	clock :  STD_LOGIC_VECTOR(15 downto 0);
signal	con :  STD_LOGIC_VECTOR(4 downto 0);
signal	time :  STD_LOGIC_VECTOR(15 downto 0);
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC;


BEGIN 



b2v_inst : second
PORT MAP(clk => clk,
		 s_overflow => SYNTHESIZED_WIRE_6,
		 s_dsph => seconhigh,
		 s_dspl => secondlow);

b2v_inst1 : minute
PORT MAP(clk => SYNTHESIZED_WIRE_0,
		 m_overflow => SYNTHESIZED_WIRE_8,
		 m_dsph => time(7 downto 4),
		 m_dspl => time(3 downto 0));

b2v_inst10 : selector12
PORT MAP(s => con(2),
		 a => keyminute,
		 x => SYNTHESIZED_WIRE_3,
		 y => SYNTHESIZED_WIRE_5);

b2v_inst11 : selector
PORT MAP(b => clkclock,
		 s => SYNTHESIZED_WIRE_1,
		 y => clockout);

b2v_inst12 : selector12
PORT MAP(s => con(3),
		 a => keyhour,
		 x => SYNTHESIZED_WIRE_4,
		 y => SYNTHESIZED_WIRE_7);

b2v_inst2 : hour
PORT MAP(clk => SYNTHESIZED_WIRE_2,
		 h_dsph => time(15 downto 12),
		 h_dspl => time(11 downto 8));

b2v_inst3 : minute
PORT MAP(clk => SYNTHESIZED_WIRE_3,
		 m_dsph => clock(7 downto 4),
		 m_dspl => clock(3 downto 0));

b2v_inst4 : hour
PORT MAP(clk => SYNTHESIZED_WIRE_4,
		 h_dsph => clock(15 downto 12),
		 h_dspl => clock(11 downto 8));

b2v_inst5 : selector
PORT MAP(a => SYNTHESIZED_WIRE_5,
		 b => SYNTHESIZED_WIRE_6,
		 s => con(0),
		 y => SYNTHESIZED_WIRE_0);

b2v_inst6 : selector217
PORT MAP(s => con(4),
		 a => time,
		 b => clock,
		 y => timeout);

b2v_inst7 : cmp32b
PORT MAP(clk => clk,
		 A => time,
		 B => clock,
		 y => SYNTHESIZED_WIRE_1);

b2v_inst8 : selector
PORT MAP(a => SYNTHESIZED_WIRE_7,
		 b => SYNTHESIZED_WIRE_8,
		 s => con(1),
		 y => SYNTHESIZED_WIRE_2);

b2v_inst9 : mode
PORT MAP(modekey => modekey,
		 OUTY => con);
clk <= lHZCLK;

END;