abs_divider_2dg.tdf

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行

--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=21 WIDTH_N=32 denominator numerator quotient remainder
--VERSION_BEGIN 7.2SP3 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION alt_u_div_g5f (denominator[20..0], numerator[31..0])
RETURNS ( den_out[20..0], quotient[31..0], remainder[20..0]);
FUNCTION lpm_abs_ur9 (data[20..0])
RETURNS ( overflow, result[20..0]);
FUNCTION lpm_abs_0s9 (data[31..0])
RETURNS ( overflow, result[31..0]);

--synthesis_resources = lut 606 
SUBDESIGN abs_divider_2dg
( 
	denominator[20..0]	:	input;
	numerator[31..0]	:	input;
	quotient[31..0]	:	output;
	remainder[20..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_g5f;
	my_abs_den : lpm_abs_ur9;
	my_abs_num : lpm_abs_0s9;
	compl_add_quot_result_int[32..0]	:	WIRE;
	compl_add_quot_cin	:	WIRE;
	compl_add_quot_dataa[31..0]	:	WIRE;
	compl_add_quot_datab[31..0]	:	WIRE;
	compl_add_quot_result[31..0]	:	WIRE;
	compl_add_rem_result_int[21..0]	:	WIRE;
	compl_add_rem_cin	:	WIRE;
	compl_add_rem_dataa[20..0]	:	WIRE;
	compl_add_rem_datab[20..0]	:	WIRE;
	compl_add_rem_result[20..0]	:	WIRE;
	diff_signs	: WIRE;
	gnd_wire	: WIRE;
	neg_quot[31..0]	: WIRE;
	neg_rem[20..0]	: WIRE;
	norm_den[20..0]	: WIRE;
	norm_num[31..0]	: WIRE;
	num_sign	: WIRE;
	protect_quotient[31..0]	: WIRE;
	protect_remainder[20..0]	: WIRE;
	vcc_wire	: WIRE;

BEGIN 
	divider.denominator[] = norm_den[];
	divider.numerator[] = norm_num[];
	my_abs_den.data[] = denominator[];
	my_abs_num.data[] = numerator[];
	compl_add_quot_result_int[] = (compl_add_quot_dataa[], compl_add_quot_cin) + (compl_add_quot_datab[], compl_add_quot_cin);
	compl_add_quot_result[] = compl_add_quot_result_int[32..1];
	compl_add_quot_cin = vcc_wire;
	compl_add_quot_dataa[] = (! protect_quotient[]);
	compl_add_quot_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
	compl_add_rem_result_int[] = (compl_add_rem_dataa[], compl_add_rem_cin) + (compl_add_rem_datab[], compl_add_rem_cin);
	compl_add_rem_result[] = compl_add_rem_result_int[21..1];
	compl_add_rem_cin = vcc_wire;
	compl_add_rem_dataa[] = (! protect_remainder[]);
	compl_add_rem_datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
	diff_signs = (numerator[31..31] $ denominator[20..20]);
	gnd_wire = B"0";
	neg_quot[] = compl_add_quot_result[];
	neg_rem[] = compl_add_rem_result[];
	norm_den[] = my_abs_den.result[];
	norm_num[] = my_abs_num.result[];
	num_sign = numerator[31..31];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
	remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
	vcc_wire = B"1";
END;
--VALID FILE