alt_u_div_o5f.tdf

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行

--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=25 WIDTH_N=32 WIDTH_Q=32 WIDTH_R=25 denominator numerator quotient remainder
--VERSION_BEGIN 7.2SP3 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);

--synthesis_resources = lut 534 
SUBDESIGN alt_u_div_o5f
( 
	den_out[24..0]	:	output;
	denominator[24..0]	:	input;
	numerator[31..0]	:	input;
	quotient[31..0]	:	output;
	remainder[24..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_lkc;
	add_sub_1 : add_sub_mkc;
	add_sub_10_result_int[11..0]	:	WIRE;
	add_sub_10_cout	:	WIRE;
	add_sub_10_dataa[10..0]	:	WIRE;
	add_sub_10_datab[10..0]	:	WIRE;
	add_sub_10_result[10..0]	:	WIRE;
	add_sub_11_result_int[12..0]	:	WIRE;
	add_sub_11_cout	:	WIRE;
	add_sub_11_dataa[11..0]	:	WIRE;
	add_sub_11_datab[11..0]	:	WIRE;
	add_sub_11_result[11..0]	:	WIRE;
	add_sub_12_result_int[13..0]	:	WIRE;
	add_sub_12_cout	:	WIRE;
	add_sub_12_dataa[12..0]	:	WIRE;
	add_sub_12_datab[12..0]	:	WIRE;
	add_sub_12_result[12..0]	:	WIRE;
	add_sub_13_result_int[14..0]	:	WIRE;
	add_sub_13_cout	:	WIRE;
	add_sub_13_dataa[13..0]	:	WIRE;
	add_sub_13_datab[13..0]	:	WIRE;
	add_sub_13_result[13..0]	:	WIRE;
	add_sub_14_result_int[15..0]	:	WIRE;
	add_sub_14_cout	:	WIRE;
	add_sub_14_dataa[14..0]	:	WIRE;
	add_sub_14_datab[14..0]	:	WIRE;
	add_sub_14_result[14..0]	:	WIRE;
	add_sub_15_result_int[16..0]	:	WIRE;
	add_sub_15_cout	:	WIRE;
	add_sub_15_dataa[15..0]	:	WIRE;
	add_sub_15_datab[15..0]	:	WIRE;
	add_sub_15_result[15..0]	:	WIRE;
	add_sub_16_result_int[17..0]	:	WIRE;
	add_sub_16_cout	:	WIRE;
	add_sub_16_dataa[16..0]	:	WIRE;
	add_sub_16_datab[16..0]	:	WIRE;
	add_sub_16_result[16..0]	:	WIRE;
	add_sub_17_result_int[18..0]	:	WIRE;
	add_sub_17_cout	:	WIRE;
	add_sub_17_dataa[17..0]	:	WIRE;