smallkeybaord.tan.qmsg

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register i\[15\] register LEDG\[3\]~reg0 142.78 MHz 7.004 ns Internal " "Info: Clock \"clk\" has Internal fmax of 142.78 MHz between source register \"i\[15\]\" and destination register \"LEDG\[3\]~reg0\" (period= 7.004 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.771 ns + Longest register register " "Info: + Longest register to register delay is 6.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i\[15\] 1 REG LCFF_X19_Y18_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y18_N17; Fanout = 3; REG Node = 'i\[15\]'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { i[15] } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.199 ns) + CELL(0.450 ns) 1.649 ns i\[12\]~450 2 COMB LCCOMB_X21_Y17_N18 1 " "Info: 2: + IC(1.199 ns) + CELL(0.450 ns) = 1.649 ns; Loc. = LCCOMB_X21_Y17_N18; Fanout = 1; COMB Node = 'i\[12\]~450'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.649 ns" { i[15] i[12]~450 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.491 ns) 2.440 ns i\[12\]~451 3 COMB LCCOMB_X21_Y17_N30 9 " "Info: 3: + IC(0.300 ns) + CELL(0.491 ns) = 2.440 ns; Loc. = LCCOMB_X21_Y17_N30; Fanout = 9; COMB Node = 'i\[12\]~451'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.791 ns" { i[12]~450 i[12]~451 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.488 ns) + CELL(0.178 ns) 3.106 ns i\[12\]~452 4 COMB LCCOMB_X20_Y17_N20 24 " "Info: 4: + IC(0.488 ns) + CELL(0.178 ns) = 3.106 ns; Loc. = LCCOMB_X20_Y17_N20; Fanout = 24; COMB Node = 'i\[12\]~452'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.666 ns" { i[12]~451 i[12]~452 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.574 ns) + CELL(0.178 ns) 3.858 ns Add0~1813 5 COMB LCCOMB_X20_Y17_N8 2 " "Info: 5: + IC(0.574 ns) + CELL(0.178 ns) = 3.858 ns; Loc. = LCCOMB_X20_Y17_N8; Fanout = 2; COMB Node = 'Add0~1813'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.752 ns" { i[12]~452 Add0~1813 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.435 ns) + CELL(0.278 ns) 5.571 ns WideOr0~138 6 COMB LCCOMB_X21_Y17_N14 6 " "Info: 6: + IC(1.435 ns) + CELL(0.278 ns) = 5.571 ns; Loc. = LCCOMB_X21_Y17_N14; Fanout = 6; COMB Node = 'WideOr0~138'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.713 ns" { Add0~1813 WideOr0~138 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.311 ns) + CELL(0.322 ns) 6.204 ns Add1~156 7 COMB LCCOMB_X21_Y17_N22 1 " "Info: 7: + IC(0.311 ns) + CELL(0.322 ns) = 6.204 ns; Loc. = LCCOMB_X21_Y17_N22; Fanout = 1; COMB Node = 'Add1~156'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.633 ns" { WideOr0~138 Add1~156 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.293 ns) + CELL(0.178 ns) 6.675 ns LEDG~76 8 COMB LCCOMB_X21_Y17_N16 1 " "Info: 8: + IC(0.293 ns) + CELL(0.178 ns) = 6.675 ns; Loc. = LCCOMB_X21_Y17_N16; Fanout = 1; COMB Node = 'LEDG~76'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.471 ns" { Add1~156 LEDG~76 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 6.771 ns LEDG\[3\]~reg0 9 REG LCFF_X21_Y17_N17 1 " "Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 6.771 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG\[3\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LEDG~76 LEDG[3]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.171 ns ( 32.06 % ) " "Info: Total cell delay = 2.171 ns ( 32.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns ( 67.94 % ) " "Info: Total interconnect delay = 4.600 ns ( 67.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { i[15] i[12]~450 i[12]~451 i[12]~452 Add0~1813 WideOr0~138 Add1~156 LEDG~76 LEDG[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "6.771 ns" { i[15] {} i[12]~450 {} i[12]~451 {} i[12]~452 {} Add0~1813 {} WideOr0~138 {} Add1~156 {} LEDG~76 {} LEDG[3]~reg0 {} } { 0.000ns 1.199ns 0.300ns 0.488ns 0.574ns 1.435ns 0.311ns 0.293ns 0.000ns } { 0.000ns 0.450ns 0.491ns 0.178ns 0.178ns 0.278ns 0.322ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.006 ns - Smallest " "Info: - Smallest clock skew is 0.006 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.828 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns clk 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns clk~clkctrl 2 COMB CLKCTRL_G11 40 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.602 ns) 2.828 ns LEDG\[3\]~reg0 3 REG LCFF_X21_Y17_N17 1 " "Info: 3: + IC(0.982 ns) + CELL(0.602 ns) = 2.828 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG\[3\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl LEDG[3]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 56.86 % ) " "Info: Total cell delay = 1.608 ns ( 56.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.220 ns ( 43.14 % ) " "Info: Total interconnect delay = 1.220 ns ( 43.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl LEDG[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[3]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.982ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.822 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns clk 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns clk~clkctrl 2 COMB CLKCTRL_G11 40 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.976 ns) + CELL(0.602 ns) 2.822 ns i\[15\] 3 REG LCFF_X19_Y18_N17 3 " "Info: 3: + IC(0.976 ns) + CELL(0.602 ns) = 2.822 ns; Loc. = LCFF_X19_Y18_N17; Fanout = 3; REG Node = 'i\[15\]'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { clk~clkctrl i[15] } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 56.98 % ) " "Info: Total cell delay = 1.608 ns ( 56.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.214 ns ( 43.02 % ) " "Info: Total interconnect delay = 1.214 ns ( 43.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { clk clk~clkctrl i[15] } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { clk {} clk~combout {} clk~clkctrl {} i[15] {} } { 0.000ns 0.000ns 0.238ns 0.976ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl LEDG[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[3]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.982ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { clk clk~clkctrl i[15] } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { clk {} clk~combout {} clk~clkctrl {} i[15] {} } { 0.000ns 0.000ns 0.238ns 0.976ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.771 ns" { i[15] i[12]~450 i[12]~451 i[12]~452 Add0~1813 WideOr0~138 Add1~156 LEDG~76 LEDG[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "6.771 ns" { i[15] {} i[12]~450 {} i[12]~451 {} i[12]~452 {} Add0~1813 {} WideOr0~138 {} Add1~156 {} LEDG~76 {} LEDG[3]~reg0 {} } { 0.000ns 1.199ns 0.300ns 0.488ns 0.574ns 1.435ns 0.311ns 0.293ns 0.000ns } { 0.000ns 0.450ns 0.491ns 0.178ns 0.178ns 0.278ns 0.322ns 0.178ns 0.096ns } "" } } { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl LEDG[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[3]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.982ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.822 ns" { clk clk~clkctrl i[15] } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.822 ns" { clk {} clk~combout {} clk~clkctrl {} i[15] {} } { 0.000ns 0.000ns 0.238ns 0.976ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "LEDG\[2\]~reg0 GPIO2\[2\] clk 7.687 ns register " "Info: tsu for register \"LEDG\[2\]~reg0\" (data pin = \"GPIO2\[2\]\", clock pin = \"clk\") is 7.687 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.553 ns + Longest pin register " "Info: + Longest pin to register delay is 10.553 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.874 ns) 0.874 ns GPIO2\[2\] 1 PIN PIN_E22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_E22; Fanout = 3; PIN Node = 'GPIO2\[2\]'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO2[2] } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.598 ns) + CELL(0.545 ns) 7.017 ns LEDG\[2\]~74 2 COMB LCCOMB_X49_Y15_N4 2 " "Info: 2: + IC(5.598 ns) + CELL(0.545 ns) = 7.017 ns; Loc. = LCCOMB_X49_Y15_N4; Fanout = 2; COMB Node = 'LEDG\[2\]~74'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.143 ns" { GPIO2[2] LEDG[2]~74 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.919 ns) + CELL(0.521 ns) 10.457 ns LEDG~75 3 COMB LCCOMB_X20_Y17_N12 1 " "Info: 3: + IC(2.919 ns) + CELL(0.521 ns) = 10.457 ns; Loc. = LCCOMB_X20_Y17_N12; Fanout = 1; COMB Node = 'LEDG~75'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.440 ns" { LEDG[2]~74 LEDG~75 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 10.553 ns LEDG\[2\]~reg0 4 REG LCFF_X20_Y17_N13 1 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 10.553 ns; Loc. = LCFF_X20_Y17_N13; Fanout = 1; REG Node = 'LEDG\[2\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LEDG~75 LEDG[2]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.036 ns ( 19.29 % ) " "Info: Total cell delay = 2.036 ns ( 19.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.517 ns ( 80.71 % ) " "Info: Total interconnect delay = 8.517 ns ( 80.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.553 ns" { GPIO2[2] LEDG[2]~74 LEDG~75 LEDG[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "10.553 ns" { GPIO2[2] {} GPIO2[2]~combout {} LEDG[2]~74 {} LEDG~75 {} LEDG[2]~reg0 {} } { 0.000ns 0.000ns 5.598ns 2.919ns 0.000ns } { 0.000ns 0.874ns 0.545ns 0.521ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.828 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns clk 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns clk~clkctrl 2 COMB CLKCTRL_G11 40 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.602 ns) 2.828 ns LEDG\[2\]~reg0 3 REG LCFF_X20_Y17_N13 1 " "Info: 3: + IC(0.982 ns) + CELL(0.602 ns) = 2.828 ns; Loc. = LCFF_X20_Y17_N13; Fanout = 1; REG Node = 'LEDG\[2\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl LEDG[2]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 56.86 % ) " "Info: Total cell delay = 1.608 ns ( 56.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.220 ns ( 43.14 % ) " "Info: Total interconnect delay = 1.220 ns ( 43.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl LEDG[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[2]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.982ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "10.553 ns" { GPIO2[2] LEDG[2]~74 LEDG~75 LEDG[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "10.553 ns" { GPIO2[2] {} GPIO2[2]~combout {} LEDG[2]~74 {} LEDG~75 {} LEDG[2]~reg0 {} } { 0.000ns 0.000ns 5.598ns 2.919ns 0.000ns } { 0.000ns 0.874ns 0.545ns 0.521ns 0.096ns } "" } } { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl LEDG[2]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[2]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.982ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk LEDG\[3\] LEDG\[3\]~reg0 9.830 ns register " "Info: tco from clock \"clk\" to destination pin \"LEDG\[3\]\" through register \"LEDG\[3\]~reg0\" is 9.830 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.828 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns clk 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns clk~clkctrl 2 COMB CLKCTRL_G11 40 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(0.602 ns) 2.828 ns LEDG\[3\]~reg0 3 REG LCFF_X21_Y17_N17 1 " "Info: 3: + IC(0.982 ns) + CELL(0.602 ns) = 2.828 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG\[3\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl LEDG[3]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 56.86 % ) " "Info: Total cell delay = 1.608 ns ( 56.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.220 ns ( 43.14 % ) " "Info: Total interconnect delay = 1.220 ns ( 43.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl LEDG[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[3]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.982ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.725 ns + Longest register pin " "Info: + Longest register to pin delay is 6.725 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LEDG\[3\]~reg0 1 REG LCFF_X21_Y17_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG\[3\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[3]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.875 ns) + CELL(2.850 ns) 6.725 ns LEDG\[3\] 2 PIN PIN_V21 0 " "Info: 2: + IC(3.875 ns) + CELL(2.850 ns) = 6.725 ns; Loc. = PIN_V21; Fanout = 0; PIN Node = 'LEDG\[3\]'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.725 ns" { LEDG[3]~reg0 LEDG[3] } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.850 ns ( 42.38 % ) " "Info: Total cell delay = 2.850 ns ( 42.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.875 ns ( 57.62 % ) " "Info: Total interconnect delay = 3.875 ns ( 57.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.725 ns" { LEDG[3]~reg0 LEDG[3] } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "6.725 ns" { LEDG[3]~reg0 {} LEDG[3] {} } { 0.000ns 3.875ns } { 0.000ns 2.850ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.828 ns" { clk clk~clkctrl LEDG[3]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.828 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[3]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.982ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.725 ns" { LEDG[3]~reg0 LEDG[3] } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "6.725 ns" { LEDG[3]~reg0 {} LEDG[3] {} } { 0.000ns 3.875ns } { 0.000ns 2.850ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "LEDG\[0\]~reg0 GPIO2\[2\] clk -3.597 ns register " "Info: th for register \"LEDG\[0\]~reg0\" (data pin = \"GPIO2\[2\]\", clock pin = \"clk\") is -3.597 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.843 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.843 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.006 ns) 1.006 ns clk 1 CLK PIN_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.244 ns clk~clkctrl 2 COMB CLKCTRL_G11 40 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.602 ns) 2.843 ns LEDG\[0\]~reg0 3 REG LCFF_X49_Y15_N13 1 " "Info: 3: + IC(0.997 ns) + CELL(0.602 ns) = 2.843 ns; Loc. = LCFF_X49_Y15_N13; Fanout = 1; REG Node = 'LEDG\[0\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.599 ns" { clk~clkctrl LEDG[0]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.608 ns ( 56.56 % ) " "Info: Total cell delay = 1.608 ns ( 56.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.235 ns ( 43.44 % ) " "Info: Total interconnect delay = 1.235 ns ( 43.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl LEDG[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[0]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.997ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.726 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.874 ns) 0.874 ns GPIO2\[2\] 1 PIN PIN_E22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_E22; Fanout = 3; PIN Node = 'GPIO2\[2\]'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { GPIO2[2] } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.578 ns) + CELL(0.178 ns) 6.630 ns LEDG~72 2 COMB LCCOMB_X49_Y15_N12 1 " "Info: 2: + IC(5.578 ns) + CELL(0.178 ns) = 6.630 ns; Loc. = LCCOMB_X49_Y15_N12; Fanout = 1; COMB Node = 'LEDG~72'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.756 ns" { GPIO2[2] LEDG~72 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 6.726 ns LEDG\[0\]~reg0 3 REG LCFF_X49_Y15_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 6.726 ns; Loc. = LCFF_X49_Y15_N13; Fanout = 1; REG Node = 'LEDG\[0\]~reg0'" {  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LEDG~72 LEDG[0]~reg0 } "NODE_NAME" } } { "smallkeybaord.v" "" { Text "E:/SopcProject/smallkeybaord/smallkeybaord.v" 9 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.148 ns ( 17.07 % ) " "Info: Total cell delay = 1.148 ns ( 17.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.578 ns ( 82.93 % ) " "Info: Total interconnect delay = 5.578 ns ( 82.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.726 ns" { GPIO2[2] LEDG~72 LEDG[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "6.726 ns" { GPIO2[2] {} GPIO2[2]~combout {} LEDG~72 {} LEDG[0]~reg0 {} } { 0.000ns 0.000ns 5.578ns 0.000ns } { 0.000ns 0.874ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.843 ns" { clk clk~clkctrl LEDG[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "2.843 ns" { clk {} clk~combout {} clk~clkctrl {} LEDG[0]~reg0 {} } { 0.000ns 0.000ns 0.238ns 0.997ns } { 0.000ns 1.006ns 0.000ns 0.602ns } "" } } { "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.726 ns" { GPIO2[2] LEDG~72 LEDG[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/quartus/bin/Technology_Viewer.qrui" "6.726 ns" { GPIO2[2] {} GPIO2[2]~combout {} LEDG~72 {} LEDG[0]~reg0 {} } { 0.000ns 0.000ns 5.578ns 0.000ns } { 0.000ns 0.874ns 0.178ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}