irtest.v

来自「关于verilog的各个基本模块的源代码」· Verilog 代码 · 共 145 行

module irtest;

reg [31:0]irin;
reg clk,reset,writeir;
wire [31:0]irout;

ir itest(irout,irin,clk,reset,writeir);

always #50 clk=~clk;

initial 
  begin
     clk=0;
     reset=1;
     writeir=0;
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0000_0011;
     writeir=1;
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0000_1100;
     writeir=1;
    
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0011_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_1100_0000;
     writeir=1;
    
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0011_0000_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_1100_0000_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0011_0000_0000_0000;
     writeir=1;
    
#100 reset=0;
     irin=32'b0000_0000_0000_0000_1100_0000_0000_0000;
     writeir=1;
    
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0000_0111;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0000_1110;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0001_1100;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0011_1000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0111_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_1110_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0001_1100_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0011_1000_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0111_0000_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_1110_0000_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0001_1100_0000_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0011_1000_0000_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0111_0000_0000_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_1110_0000_0000_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0000_1111;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0001_1110;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0011_1100;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_0111_1000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0000_1111_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0001_1110_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0011_1100_0000;
     writeir=1;
     
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_0111_1000_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0000_1111_0000_0000;
     writeir=1;
      
#100 reset=0;
     irin=32'b0000_0000_0000_0000_0001_1110_0000_0000;
     writeir=1;
      
#200 $stop;
  end
endmodule