pc.v

关于verilog的各个基本模块的源代码

module pc(pcout,pcin,writepc,clk,rst);

output [4:0] pcout;
input  [4:0] pcin;
input writepc,clk,rst;

reg [4:0] pcout;

always @(rst)
  begin 
    if(rst)
        pcout<=5'b00000;
    else
        pcout<=pcout;
  end

always @(posedge clk)
  begin
   if(writepc)
     pcout<=pcin;
   else
     pcout<=pcout;
  end
endmodule