zerostore.v

来自「关于verilog的各个基本模块的源代码」· Verilog 代码 · 共 15 行

module zerostore(a,writezero,b);

input a,writezero;
output b;

reg b;

always @(writezero or a or b)

case(writezero)
1'd0: b=b;
1'd1: b=a;
endcase

endmodule