decodertest.v

来自「关于verilog的各个基本模块的源代码」· Verilog 代码 · 共 49 行

module decodertest;


wire [31:0] decoderout;
reg [4:0] waddr;

decoder d(decoderout,waddr);

initial
  begin
#50 waddr=5'd0;
#50 waddr=5'd1;
#50 waddr=5'd2;
#50 waddr=5'd3;
#50 waddr=5'd4;
#50 waddr=5'd5;
#50 waddr=5'd6;
#50 waddr=5'd7;
#50 waddr=5'd8;
#50 waddr=5'd9;
#50 waddr=5'd10;
#50 waddr=5'd11;
#50 waddr=5'd12;
#50 waddr=5'd13;
#50 waddr=5'd14;
#50 waddr=5'd15;
#50 waddr=5'd16;
#50 waddr=5'd17;
#50 waddr=5'd18;
#50 waddr=5'd19;
#50 waddr=5'd20;
#50 waddr=5'd21;
#50 waddr=5'd22;
#50 waddr=5'd23;
#50 waddr=5'd24;
#50 waddr=5'd25;
#50 waddr=5'd26;
#50 waddr=5'd27;
#50 waddr=5'd28;
#50 waddr=5'd29;
#50 waddr=5'd30;
#50 waddr=5'd31;

#200 $stop;
	end  
endmodule