mux21_5test.v

关于verilog的各个基本模块的源代码

module mux21_5test;

reg [4:0]pcout,aluout;
reg selldst;
wire [4:0] address;

mux21_5 mux2(address,pcout,aluout,selldst);

initial
  begin
#50  pcout=5'b00101;	
     aluout=5'b11010;
#50  selldst=0;
#50  selldst=1;
#200 $stop;
  end

endmodule