controltest.v

关于verilog的各个基本模块的源代码

module controltest;

reg clk,rst,zero;
reg [5:0] opcode;
wire writepc,selldst,writemem,writeir,selload,selst,writereg,selalua,writezero;
wire [1:0] selalub,aluop;

control con(clk,rst,zero,opcode,writepc,selldst,writemem,writeir,selload,selst,writereg,selalua,selalub,aluop,writezero);

always #50 clk=~clk;
initial
  begin
    rst=1;
    clk=0;
#50 rst=0;
    opcode=6'd0;
    zero=1;
#50 rst=0;
    opcode=6'd1;
    zero=1;
#50 rst=0;
    opcode=6'd2;
    zero=1;
#50 rst=0;
    opcode=6'd3;
    zero=1;
#50 rst=0;
    opcode=6'd4;
    zero=1;
#50 rst=0;
    opcode=6'd5;
    zero=1;
#50 rst=0;
    opcode=6'd6;
    zero=1;
#50 rst=0;
    opcode=6'd7;
    zero=1;
#50 rst=0;
    opcode=6'd8;
    zero=1;
#50 rst=0;
    opcode=6'd9;
    zero=1;
#50 rst=0;
    opcode=6'd10;
    zero=1;
#50 rst=0;
    opcode=6'd11;
    zero=1;
#50 rst=0;
    opcode=6'd12;
    zero=1;
#50 rst=0;
    opcode=6'd0;
    zero=0;
#50 rst=0;
    opcode=6'd1;
    zero=0;
#50 rst=0;
    opcode=6'd2;
    zero=0;
#50 rst=0;
    opcode=6'd3;
    zero=0;
#50 rst=0;
    opcode=6'd4;
    zero=0;
#50 rst=0;
    opcode=6'd5;
    zero=0;
#50 rst=0;
    opcode=6'd6;
    zero=1;
#50 rst=0;
    opcode=6'd7;
    zero=0;
#50 rst=0;
    opcode=6'd8;
    zero=0;
#50 rst=0;
    opcode=6'd9;
    zero=1;
#50 rst=0;
    opcode=6'd10;
    zero=0;
#50 rst=0;
    opcode=6'd11;
    zero=1;
#50 rst=0;
    opcode=6'd12;
    zero=0;
#50 rst=0;
    opcode=6'd0;
    zero=1;
#50 rst=0;
    opcode=6'd1;
    zero=0;
#50 rst=0;
    opcode=6'd2;
    zero=0;
#50 rst=0;
    opcode=6'd3;
    zero=0;
#50 rst=0;
    opcode=6'd4;
    zero=0;
#50 rst=0;
    opcode=6'd5;
    zero=0;
#50 rst=0;
    opcode=6'd6;
    zero=0;
#50 rst=0;
    opcode=6'd7;
    zero=1;
#50 rst=0;
    opcode=6'd8;
    zero=0;
#50 rst=0;
    opcode=6'd9;
    zero=0;
#50 rst=0;
    opcode=6'd10;
    zero=0;
#50 rst=0;
    opcode=6'd11;
    zero=0;
#50 rst=0;
    opcode=6'd12;
    zero=0;
#50 $stop;
end

endmodule