registerfiletest.v

关于verilog的各个基本模块的源代码

module registerfiletest;

wire [31:0]q11,q22;
reg [31:0]data;
reg [4:0]waddr;
reg [4:0]raddr1,raddr2;
reg clk,reset,we;

registerfile r(q11,q22,data,clk,reset,we,waddr,raddr1,raddr2);

always #50 clk=~clk;

initial
   begin 
     clk=0;
     reset=1;
     we=0;
#100 reset=0;
     data=32'b0000_0000_0000_0011_0000_1101_1100_0011;
     we=1;
     waddr=5'd0;
#100 reset=0;
     data=32'b0000_0000_0000_1100_0000_1101_1100_0011;
     we=1;
     waddr=5'd1;
#100 reset=0;
     data=32'b0000_0000_0011_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd2;
#100 reset=0;
     data=32'b0000_0000_1100_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd3;
#100 reset=0;
     data=32'b0000_0011_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd4;
#100 reset=0;
     data=32'b0000_1100_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd5;
#100 reset=0;
     data=32'b0011_0000_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd6;
#100 reset=0;
     data=32'b1100_0000_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd7;
#100 reset=0;
     data=32'b0000_0000_0000_0111_0000_1101_1100_0011;
     we=1;
     waddr=5'd8;
#100 reset=0;
     data=32'b0000_0000_0000_1110_0000_1101_1100_0011;
     we=1;
     waddr=5'd9;
#100 reset=0;
     data=32'b0000_0000_0001_1100_0000_1101_1100_0011;
     we=1;
     waddr=5'd10;
#100 reset=0;
     data=32'b0000_0000_0011_1000_0000_1101_1100_0011;
     we=1;
     waddr=5'd11;
#100 reset=0;
     data=32'b0000_0000_0111_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd12;
#100 reset=0;
     data=32'b0000_0000_1110_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd13;
#100 reset=0;
     data=32'b0000_0001_1100_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd14;
#100 reset=0;
     data=32'b0000_0011_1000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd15;
#100 reset=0;
     data=32'b0000_0111_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd16;
#100 reset=0;
     data=32'b0000_1110_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd17;
#100 reset=0;
     data=32'b0001_1100_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd18;
#100 reset=0;
     data=32'b0011_1000_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd19;
#100 reset=0;
     data=32'b0111_0000_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd20;
#100 reset=0;
     data=32'b1110_0000_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd21;
#100 reset=0;
     data=32'b0000_0000_0000_1111_0000_1101_1100_0011;
     we=1;
     waddr=5'd22;
#100 reset=0;
     data=32'b0000_0000_0001_1110_0000_1101_1100_0011;
     we=1;
     waddr=5'd23;
#100 reset=0;
     data=32'b0000_0000_0011_1100_0000_1101_1100_0011;
     we=1;
     waddr=5'd24;
#100 reset=0;
     data=32'b0000_0000_0111_1000_0000_1101_1100_0011;
     we=1;
     waddr=5'd25;
#100 reset=0;
     data=32'b0000_0000_1111_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd26;
#100 reset=0;
     data=32'b0000_0001_1110_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd27;
#100 reset=0;
     data=32'b0000_0011_1100_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd28;
#100 reset=0;
     data=32'b0000_0111_1000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd29;
#100 reset=0;
     data=32'b0000_1111_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd30;
#100 reset=0;
     data=32'b0001_1110_0000_0000_0000_1101_1100_0011;
     we=1;
     waddr=5'd31;
#100 reset=0;
     we=0;
		raddr1=5'd0;
#100 reset=0;
     we=0;
		raddr2=5'd1;
#100 reset=0;
     we=0;
		raddr1=5'd2;
#100 reset=0;
     we=0;
		raddr2=5'd3;
#100 reset=0;
     we=0;
		raddr1=5'd4;
#100 reset=0;
     we=0;
		raddr1=5'd5;
#100 reset=0;
     we=0;
		raddr2=5'd6;
#100 reset=0;
     we=0;
		raddr1=5'd7;
#100 reset=0;
     we=0;
		raddr2=5'd8;
#100 reset=0;
     we=0;
		raddr1=5'd9;
#100 reset=0;
     we=0;
		raddr2=5'd10;
#100 reset=0;
     we=0;
		raddr2=5'd11;
#100 reset=0;
     we=0;
		raddr1=5'd12;
#100 reset=0;
     we=0;
		raddr1=5'd13;
#100 reset=0;
     we=0;
		raddr2=5'd14;
#100 reset=0;
     we=0;
		raddr2=5'd15;
#100 reset=0;
     we=0;
		raddr1=5'd16;
#100 reset=0;
     we=0;
		raddr1=5'd17;
#100 reset=0;
     we=0;
		raddr2=5'd18;
#100 reset=0;
     we=0;
		raddr2=5'd19;
#100 reset=0;
     we=0;
		raddr1=5'd20;
#100 reset=0;
     we=0;
		raddr2=5'd21;
#100 reset=0;
     we=0;
		raddr1=5'd22;
#100 reset=0;
     we=0;
		raddr2=5'd23;
#100 reset=0;
     we=0;
		raddr2=5'd24;
#100 reset=0;
     we=0;
		raddr1=5'd25;
#100 reset=0;
     we=0;
		raddr1=5'd26;
#100 reset=0;
     we=0;
		raddr1=5'd27;
#100 reset=0;
     we=0;
		raddr2=5'd28;
#100 reset=0;
     we=0;
		raddr1=5'd29;
#100 reset=0;
     we=0;
		raddr2=5'd30;
#100 reset=0;
     we=0;
		raddr1=5'd31;
#200 $stop;
	end  
endmodule