dff.v

关于verilog的各个基本模块的源代码

module dff(q,data,clk,reset,en);
output q;
input data,clk,reset,en;

reg q;

always @ (posedge clk)
	begin
		if (reset)
			q=0;
		else if (en)
					q=data;
				else 
					q=q;
	end
endmodule