registertest.v

关于verilog的各个基本模块的源代码

module registertest;

wire [31:0]q;
reg [31:0]data;
reg clk,reset,en;

register r(q,data,clk,reset,en);

always #50 clk=~clk;

initial
	begin
		clk=0;
		reset=0;
		en=0;
#20  reset=1;
     data=32'b0000_1111_0010_1100_0010_1100_1101_1111;
     en=1;
#100 reset=0;
#100 data=32'b0000_0000_0000_0000_0010_1100_0010_1100;
#100 en=0;
     data=32'b1010_1100_1100_0011_1111_0010_1100_0010;
#100 en=1;
     data=32'b0010_1101_0010_1010_0010_1100_1101_1111;
#200 $stop;
	end  
endmodule