mult.vhd

移位乘法器的输入为两个4位操作数a和b

library ieee;
use ieee.std_logic_1164.all;

entity mult is
    port(   a,b: in std_logic_vector(3 downto 0);
           clk, stb: in std_logic;
         result: out std_logic_vector(7 downto 0);
           done: out std_logic) ;
end mult;


architecture arch of mult is
    signal init,shift,lsb,stop,add :std_logic;
    signal accout,addout,sraout,srbout:std_logic_vector (7 downto 0);

    begin
	controller: process
	begin
	wait until clk'event and clk='1'and stb='1';
        done<='0'; 
	init<='1'; 
	shift<='0';
	add<='0';
	result<="00000000";
	

	wait until clk'event and clk='1';
	init<='0';
       
      	runloop: while(stop/='1') loop
             wait until clk'event and clk='1';
             if lsb='1'  then
                   wait until clk'event and clk='1';
                   add<='1';
                   wait until clk'event and clk='1';
                   add<='0';
                   shift<='1';
                   wait until clk'event and clk='1';
	     else
                   wait until clk'event and clk='1';
		   shift<='1';
                   wait until clk'event and clk='1';
	   end if;
	   shift<='0';
	   end loop runloop;
	   done<='1';
	    result<=accout;
	   end process;


	srra:process                   --乘数右移
	begin
              wait until clk'event and clk='1';
	      if init='1' then
	      sraout<="0000"&a;
             
	      elsif shift='1'  then
	      sraout<='0'&sraout(7 downto 1);
	      end if;
	end process srra;

	nora:process(sraout)
	begin 
             stop<=not(sraout(0)or sraout(1)or sraout(2)or sraout(3)or sraout(4)or sraout(5)or sraout(6)or sraout(7));
	      lsb<=sraout(0);
	      end process nora;



        srrb:process             --被乘数 左移
        begin
              wait until clk'event and clk='1';
	      if init='1' then
		      srbout<="0000"&b;
	      elsif shift='1'  then
		      srbout<=srbout(6 downto 0)&'0';
	      end if;
	      end process srrb;


       adder:process(srbout)
          variable sum,tmp1,tmp2: std_logic_vector (7 downto 0);
	  variable carry:std_logic;
          begin
               tmp1:=accout;
	       tmp2:=srbout;
	       carry:='0';
	       for i in 0 to 7 loop
		       sum(i):=tmp1(i) xor tmp2(i) xor carry;
		       carry:=(tmp1(i) and tmp2(i)) or (tmp2(i) and carry) or (tmp2(i) and carry);
		      end loop;
		     addout<=sum;
               end process adder;



         acc:process
	 begin
               wait until clk'event and clk='1';
	       if init='1' then
		       accout<="00000000";
	       elsif add='1' then
		       accout<=addout;
	       end if;
                   
	       end process acc;


	       end arch;