cy8c29466_test.lst
来自「塞扑拉思 psoc spi模块 作为master 的应用程序.」· LST 代码 · 共 923 行 · 第 1/5 页
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(0294) M8C_SetBank0
(0295) M8C_ClearWDTAndSleep ; Reset the sleep timer to get a full second
(0296) or reg[INT_MSK0], INT_MSK0_SLEEP ; Enable latching of SleepTimer interrupt
(0297) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0298) .WaitFor1s:
(0299) tst reg[INT_CLR0], INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0300) jz .WaitFor1s ; Interrupt will latch but will not dispatch
(0301) ; since interrupts are not globally enabled
(0302) ELSE ; !( SELECT_32K & WAIT_FOR_32K )
(0303) ; Either no ECO, or waiting for stable clock is to be done in main
0084: 71 10 OR F,16 (0304) M8C_SetBank1
0086: 62 E0 02 MOV REG[224],2 (0305) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
0089: 70 EF AND F,239 (0306) M8C_SetBank0
008B: 62 E3 38 MOV REG[227],56 (0307) M8C_ClearWDTAndSleep ; Reset the watch dog
(0308)
(0309) ENDIF ;( SELECT_32K & WAIT_FOR_32K )
(0310)
(0311) IF ( PLL_MODE )
(0312) ; Crystal is now fully operational (assuming WAIT_FOR_32K was enabled).
(0313) ; Now start up PLL if selected, and wait 16 msec for it to stabilize.
(0314) ;
(0315) M8C_SetBank1
(0316) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_3MHz)
(0317) M8C_SetBank0
(0318) M8C_ClearWDTAndSleep ; Reset the sleep timer to get full period
(0319) mov reg[INT_VC], 0 ; Clear all pending interrupts
(0320)
(0321) .WaitFor16ms:
(0322) tst reg[INT_CLR0],INT_MSK0_SLEEP ; Test the SleepTimer Interrupt Status
(0323) jz .WaitFor16ms
(0324) M8C_SetBank1 ; continue boot at CPU Speed of SYSCLK/2
(0325) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_12MHz)
(0326) M8C_SetBank0
(0327)
(0328) IF ( WAIT_FOR_32K )
(0329) ELSE ; !( WAIT_FOR_32K )
(0330) ; Option settings (PLL-Yes, ECO-No) are incompatible - force a syntax error
(0331) ERROR_PSoC Disabling WAIT_FOR_32K requires that the PLL_Lock must be enabled in user code.
(0332) ENDIF ;(WAIT_FOR_32K)
(0333) ENDIF ;(PLL_MODE)
(0334)
(0335) ;------------------------
(0336) ; Close CT leakage path.
(0337) ;------------------------
008E: 62 71 05 MOV REG[113],5 (0338) mov reg[ACB00CR0], 05h
0091: 62 75 05 MOV REG[117],5 (0339) mov reg[ACB01CR0], 05h
0094: 62 79 05 MOV REG[121],5 (0340) mov reg[ACB02CR0], 05h
0097: 62 7D 05 MOV REG[125],5 (0341) mov reg[ACB03CR0], 05h
(0342)
(0343) ;---------------------------------------------
(0344) ; Enter the Large Memory Model, if applicable
(0345) ;---------------------------------------------
(0346) IF ( SYSTEM_LARGE_MEMORY_MODEL )
009A: 62 D1 07 MOV REG[209],7 (0347) RAM_SETPAGE_STK SYSTEM_STACK_PAGE ; relocate stack page ...
009D: 50 00 MOV A,0 (0348) mov A, SYSTEM_STACK_BASE_ADDR ; and offset, if any
009F: 4E SWAP SP,A (0349) swap A, SP
00A0: 62 D3 07 MOV REG[211],7 (0350) RAM_SETPAGE_IDX2STK ; initialize other page pointers
00A3: 62 D0 00 MOV REG[208],0 (0351) RAM_SETPAGE_CUR 0
00A6: 62 D5 00 MOV REG[213],0 (0352) RAM_SETPAGE_MVW 0
00A9: 62 D4 00 MOV REG[212],0 (0353) RAM_SETPAGE_MVR 0
(0354)
(0355) IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
00AC: 71 C0 OR F,192 (0356) or F, FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
(0357) ELSE
(0358) or F, FLAG_PGMODE_10b ; LMM w/ independent IndexPage
(0359) ENDIF ; SYSTEM_IDXPG_TRACKS_STK_PP
(0360) ELSE
(0361) mov A, __ramareas_end ; Set top of stack to end of used RAM
(0362) swap SP, A
(0363) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0364)
(0365) ;-------------------------
(0366) ; Load Base Configuration
(0367) ;-------------------------
(0368) ; Load global parameter settings and load the user modules in the
(0369) ; base configuration. Exceptions: (1) Leave CPU Speed fast as possible
(0370) ; to minimize start up time; (2) We may still need to play with the
(0371) ; Sleep Timer.
(0372) ;
00AE: 7C 03 4E LCALL 0x034E (0373) lcall LoadConfigInit
(0374)
(0375) ;-----------------------------------
(0376) ; Initialize C Run-Time Environment
(0377) ;-----------------------------------
(0378) IF ( C_LANGUAGE_SUPPORT )
(0379) IF ( SYSTEM_SMALL_MEMORY_MODEL )
(0380) mov A,0 ; clear the 'bss' segment to zero
(0381) mov [__r0],<__bss_start
(0382) BssLoop:
(0383) cmp [__r0],<__bss_end
(0384) jz BssDone
(0385) mvi [__r0],A
(0386) jmp BssLoop
(0387) BssDone:
(0388) mov A,>__idata_start ; copy idata to data segment
(0389) mov X,<__idata_start
(0390) mov [__r0],<__data_start
(0391) IDataLoop:
(0392) cmp [__r0],<__data_end
(0393) jz C_RTE_Done
(0394) push A
(0395) romx
(0396) mvi [__r0],A
(0397) pop A
(0398) inc X
(0399) adc A,0
(0400) jmp IDataLoop
(0401)
(0402) ENDIF ; SYSTEM_SMALL_MEMORY_MODEL
(0403)
(0404) IF ( SYSTEM_LARGE_MEMORY_MODEL )
00B1: 62 D0 00 MOV REG[208],0 (0405) mov reg[CUR_PP], >__r0 ; force direct addr mode instructions
(0406) ; to use the Virtual Register page.
(0407)
(0408) ; Dereference the constant (flash) pointer pXIData to access the start
(0409) ; of the extended idata area, "xidata." Xidata follows the end of the
(0410) ; text segment and may have been relocated by the Code Compressor.
(0411) ;
00B4: 50 01 MOV A,1 (0412) mov A, >__pXIData ; Get the address of the flash
00B6: 57 A0 MOV X,160 (0413) mov X, <__pXIData ; pointer to the xidata area.
00B8: 08 PUSH A (0414) push A
00B9: 28 ROMX (0415) romx ; get the MSB of xidata's address
00BA: 53 07 MOV [__r0],A (0416) mov [__r0], A
00BC: 18 POP A (0417) pop A
00BD: 75 INC X (0418) inc X
00BE: 09 00 ADC A,0 (0419) adc A, 0
00C0: 28 ROMX (0420) romx ; get the LSB of xidata's address
00C1: 4B SWAP A,X (0421) swap A, X
00C2: 51 07 MOV A,[7] (0422) mov A, [__r0] ; pXIData (in [A,X]) points to the
(0423) ; XIData structure list in flash
00C4: 80 04 JMP 0x00C9 (0424) jmp .AccessStruct
(0425)
(0426) ; Unpack one element in the xidata "structure list" that specifies the
(0427) ; values of C variables. Each structure contains 3 member elements.
(0428) ; The first is a pointer to a contiguous block of RAM to be initial-
(0429) ; ized. Blocks are always 255 bytes or less in length and never cross
(0430) ; RAM page boundaries. The list terminates when the MSB of the pointer
(0431) ; contains 0xFF. There are two formats for the struct depending on the
(0432) ; value in the second member element, an unsigned byte:
(0433) ; (1) If the value of the second element is non-zero, it represents
(0434) ; the 'size' of the block of RAM to be initialized. In this case, the
(0435) ; third member of the struct is an array of bytes of length 'size' and
(0436) ; the bytes are copied to the block of RAM.
(0437) ; (2) If the value of the second element is zero, the block of RAM is
(0438) ; to be cleared to zero. In this case, the third member of the struct
(0439) ; is an unsigned byte containing the number of bytes to clear.
(0440)
(0441) .AccessNextStructLoop:
00C6: 75 INC X (0442) inc X ; pXIData++
00C7: 09 00 ADC A,0 (0443) adc A, 0
(0444) .AccessStruct: ; Entry point for first block
(0445) ;
(0446) ; Assert: pXIData in [A,X] points to the beginning of an XIData struct.
(0447) ;
00C9: 62 E3 00 MOV REG[227],0 (0448) M8C_ClearWDT ; Clear the watchdog for long inits
00CC: 08 PUSH A (0449) push A
00CD: 28 ROMX (0450) romx ; MSB of RAM addr (CPU.A <- *pXIData)
00CE: 60 D5 MOV REG[213],A (0451) mov reg[MVW_PP], A ; for use with MVI write operations
00D0: 74 INC A (0452) inc A ; End of Struct List? (MSB==0xFF?)
00D1: A0 4B JZ 0x011D (0453) jz .C_RTE_WrapUp ; Yes, C runtime environment complete
00D3: 18 POP A (0454) pop A ; restore pXIData to [A,X]
00D4: 75 INC X (0455) inc X ; pXIData++
00D5: 09 00 ADC A,0 (0456) adc A, 0
00D7: 08 PUSH A (0457) push A
00D8: 28 ROMX (0458) romx ; LSB of RAM addr (CPU.A <- *pXIData)
00D9: 53 07 MOV [__r0],A (0459) mov [__r0], A ; RAM Addr now in [reg[MVW_PP],[__r0]]
00DB: 18 POP A (0460) pop A ; restore pXIData to [A,X]
00DC: 75 INC X (0461) inc X ; pXIData++ (point to size)
00DD: 09 00 ADC A,0 (0462) adc A, 0
00DF: 08 PUSH A (0463) push A
00E0: 28 ROMX (0464) romx ; Get the size (CPU.A <- *pXIData)
00E1: A0 1C JZ 0x00FE (0465) jz .ClearRAMBlockToZero ; If Size==0, then go clear RAM
00E3: 53 06 MOV [__r1],A (0466) mov [__r1], A ; else downcount in __r1
00E5: 18 POP A (0467) pop A ; restore pXIData to [A,X]
(0468)
(0469) .CopyNextByteLoop:
(0470) ; For each byte in the structure's array member, copy from flash to RAM.
(0471) ; Assert: pXIData in [A,X] points to previous byte of flash source;
(0472) ; [reg[MVW_PP],[__r0]] points to next RAM destination;
(0473) ; __r1 holds a non-zero count of the number of bytes remaining.
(0474) ;
00E6: 75 INC X (0475) inc X ; pXIData++ (point to next data byte)
00E7: 09 00 ADC A,0 (0476) adc A, 0
00E9: 08 PUSH A (0477) push A
00EA: 28 ROMX (0478) romx ; Get the data value (CPU.A <- *pXIData)
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