cy8c29466_test.lst
来自「塞扑拉思 psoc spi模块 作为master 的应用程序.」· LST 代码 · 共 923 行 · 第 1/5 页
LST
923 行
0031: 30 HALT
0032: 30 HALT
0033: 30 HALT
(0151)
(0152) org 34h ;PSoC Block DBB11 Interrupt Vector
(0153) // call void_handler
0034: 7E RETI (0154) reti
0035: 30 HALT
0036: 30 HALT
0037: 30 HALT
(0155)
(0156) org 38h ;PSoC Block DCB12 Interrupt Vector
(0157) // call void_handler
0038: 7E RETI (0158) reti
0039: 30 HALT
003A: 30 HALT
003B: 30 HALT
(0159)
(0160) org 3Ch ;PSoC Block DCB13 Interrupt Vector
(0161) // call void_handler
003C: 7E RETI (0162) reti
003D: 30 HALT
003E: 30 HALT
003F: 30 HALT
(0163)
(0164) org 40h ;PSoC Block DBB20 Interrupt Vector
(0165) // call void_handler
0040: 7E RETI (0166) reti
0041: 30 HALT
0042: 30 HALT
0043: 30 HALT
(0167)
(0168) org 44h ;PSoC Block DBB21 Interrupt Vector
(0169) // call void_handler
0044: 7E RETI (0170) reti
0045: 30 HALT
0046: 30 HALT
0047: 30 HALT
(0171)
(0172) org 48h ;PSoC Block DCB22 Interrupt Vector
(0173) // call void_handler
0048: 7E RETI (0174) reti
0049: 30 HALT
004A: 30 HALT
004B: 30 HALT
(0175)
(0176) org 4Ch ;PSoC Block DCB23 Interrupt Vector
(0177) // call void_handler
004C: 7E RETI (0178) reti
004D: 30 HALT
004E: 30 HALT
004F: 30 HALT
(0179)
(0180) org 50h ;PSoC Block DBB30 Interrupt Vector
(0181) // call void_handler
0050: 7E RETI (0182) reti
0051: 30 HALT
0052: 30 HALT
0053: 30 HALT
(0183)
(0184) org 54h ;PSoC Block DBB31 Interrupt Vector
(0185) // call void_handler
0054: 7E RETI (0186) reti
0055: 30 HALT
0056: 30 HALT
0057: 30 HALT
(0187)
(0188) org 58h ;PSoC Block DCB32 Interrupt Vector
(0189) // call void_handler
0058: 7E RETI (0190) reti
0059: 30 HALT
005A: 30 HALT
005B: 30 HALT
(0191)
(0192) org 5Ch ;PSoC Block DCB33 Interrupt Vector
(0193) // call void_handler
005C: 7E RETI (0194) reti
005D: 30 HALT
005E: 30 HALT
005F: 30 HALT
(0195)
(0196) org 60h ;PSoC I2C Interrupt Vector
(0197) // call void_handler
0060: 7E RETI (0198) reti
0061: 30 HALT
0062: 30 HALT
0063: 30 HALT
(0199)
(0200) org 64h ;Sleep Timer Interrupt Vector
(0201) // call void_handler
0064: 7E RETI (0202) reti
0065: 30 HALT
0066: 30 HALT
0067: 30 HALT
(0203)
(0204) ;-----------------------------------------------------------------------------
(0205) ; Start of Execution.
(0206) ;-----------------------------------------------------------------------------
(0207) ; The Supervisory ROM SWBootReset function has already completed the
(0208) ; calibrate1 process, loading trim values for 5 volt operation.
(0209) ;
(0210) org 68h
(0211) __Start:
(0212)
(0213) ; initialize SMP values for voltage stabilization, if required,
(0214) ; leaving power-on reset (POR) level at the default (low) level, at
(0215) ; least for now.
(0216) ;
0068: 71 10 OR F,16 (0217) M8C_SetBank1
006A: 62 E3 87 MOV REG[227],135 (0218) mov reg[VLT_CR], SWITCH_MODE_PUMP_JUST | LVD_TBEN_JUST | TRIP_VOLTAGE_JUST
006D: 70 EF AND F,239 (0219) M8C_SetBank0
(0220)
(0221) ; %53%20%46%46% Apply Erratum 001-05137 workaround
006F: 50 20 MOV A,32 (0222) mov A, 20h
0071: 28 ROMX (0223) romx
0072: 50 40 MOV A,64 (0224) mov A, 40h
0074: 28 ROMX (0225) romx
0075: 50 60 MOV A,96 (0226) mov A, 60h
0077: 28 ROMX (0227) romx
(0228) ; %45%20%46%46% End workaround
(0229)
(0230) IF ( WATCHDOG_ENABLE ) ; WDT selected in Global Params
(0231) M8C_EnableWatchDog
(0232) ENDIF
(0233)
(0234) IF ( SELECT_32K )
(0235) or reg[CPU_SCR1], CPU_SCR1_ECO_ALLOWED ; ECO will be used in this project
(0236) ELSE
0078: 41 FE FB AND REG[254],251 (0237) and reg[CPU_SCR1], ~CPU_SCR1_ECO_ALLOWED ; Prevent ECO from being enabled
(0238) ENDIF
(0239)
(0240) ;---------------------------
(0241) ; Set up the Temporary stack
(0242) ;---------------------------
(0243) ; A temporary stack is set up for the SSC instructions.
(0244) ; The real stack start will be assigned later.
(0245) ;
(0246) _stack_start: equ 80h
007B: 50 80 MOV A,128 (0247) mov A, _stack_start ; Set top of stack to end of used RAM
007D: 4E SWAP SP,A (0248) swap SP, A ; This is only temporary if going to LMM
(0249)
(0250) ;-----------------------------------------------
(0251) ; Set Power-related Trim & the AGND Bypass bit.
(0252) ;-----------------------------------------------
(0253)
(0254) IF ( POWER_SETTING & POWER_SET_5V0) ; *** 5.0 Volt operation ***
(0255) IF ( POWER_SETTING & POWER_SET_SLOW_IMO) ; *** 6MHZ Main Oscillator ***
(0256) or reg[CPU_SCR1], CPU_SCR1_SLIMO
(0257) M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_5V_6MHZ, 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
(0258) ELSE ; *** 12MHZ Main Oscillator ***
(0259) IF ( AGND_BYPASS )
(0260) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0261) ; The 5V trim has already been set, but we need to update the AGNDBYP
(0262) ; bit in the write-only BDG_TR register. Recalculate the register
(0263) ; value using the proper trim values.
(0264) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0265) M8SSC_SetTableVoltageTrim 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
(0266) ENDIF
(0267) ENDIF
(0268) ENDIF ; 5.0 V Operation
(0269)
(0270) IF ( POWER_SETTING & POWER_SET_3V3) ; *** 3.3 Volt operation ***
(0271) IF ( POWER_SETTING & POWER_SET_SLOW_IMO) ; *** 6MHZ Main Oscillator ***
(0272) or reg[CPU_SCR1], CPU_SCR1_SLIMO
(0273) M8SSC_Set2TableTrims 2, SSCTBL2_TRIM_IMO_3V_6MHZ, 1, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
(0274) ELSE ; *** 12MHZ Main Oscillator ***
(0275) M8SSC_SetTableTrims 1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGND_BYPASS_JUST
(0276) ENDIF
(0277) ENDIF ; 3.3 Volt Operation
(0278)
007E: 55 F8 00 MOV [248],0 (0279) mov [bSSC_KEY1], 0 ; Lock out Flash and Supervisiory operations
0081: 55 F9 00 MOV [249],0 (0280) mov [bSSC_KEYSP], 0
(0281)
(0282) ;---------------------------------------
(0283) ; Initialize Crystal Oscillator and PLL
(0284) ;---------------------------------------
(0285)
(0286) IF ( SELECT_32K & WAIT_FOR_32K )
(0287) ; If the user has requested the External Crystal Oscillator (ECO) then turn it
(0288) ; on and wait for it to stabilize and the system to switch over to it. The PLL
(0289) ; is left off. Set the SleepTimer period is set to 1 sec to time the wait for
(0290) ; the ECO to stabilize.
(0291) ;
(0292) M8C_SetBank1
(0293) mov reg[OSC_CR0], (SELECT_32K_JUST | OSC_CR0_SLEEP_1Hz | OSC_CR0_CPU_12MHz)
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