ch_fir.sim.rpt

来自「基于分布式算法的FPGA实现的FIR滤波器源码」· RPT 代码 · 共 376 行 · 第 1/5 页

; |CH_FIR|data[2]                                                                                         ; |CH_FIR|data[2]                                                                                   ; combout          ;
; |CH_FIR|clk~clkctrl                                                                                     ; |CH_FIR|clk~clkctrl                                                                               ; outclk           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[9]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[9]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[8]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[8]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[7]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[7]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[5]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[5]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[4]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[4]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[3]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[3]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[2]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[2]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[1]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[1]~feeder                                                             ; combout          ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[0]~feeder                                                                   ; |CH_FIR|LATCH8:inst1|Q_TEMP[0]~feeder                                                             ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[1]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[1]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[1]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[1]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[1]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[1]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[1]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[1]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[1]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[1]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|do~feeder                 ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|do~feeder           ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|do~feeder                 ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|do~feeder           ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|do~feeder                 ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|do~feeder           ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[8]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[8]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[8]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[8]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[8]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[8]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[8]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[8]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[8]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[8]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[7]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[7]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[7]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[7]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[7]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[7]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[7]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[7]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[7]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[7]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[7]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[7]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[6]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[6]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[6]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[6]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[6]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[6]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[6]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[6]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[6]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[6]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[6]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[6]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[6]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[6]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[5]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[5]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[5]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[5]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[5]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[5]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[5]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[5]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[5]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[5]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[4]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[4]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[4]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[4]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[4]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[4]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[4]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[4]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[4]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[4]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[3]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[3]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[3]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[3]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[3]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[3]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[3]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[3]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[3]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[3]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[2]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[2]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[2]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[2]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[2]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[2]~feeder         ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[2]~feeder               ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[2]~feeder         ; combout          ;
+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                   ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                  ; Output Port Name                                                                           ; Output Port Type ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx|Cin     ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx|Cin     ; regout           ;
; |CH_FIR|controller:inst3|cc:inst|present_state.s0~42                                       ; |CH_FIR|controller:inst3|cc:inst|present_state.s0~42                                       ; combout          ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx|Cin~130 ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx|Cin~130 ; combout          ;
; |CH_FIR|input_process:inst|ptos:inst2|q_temP[3]                                            ; |CH_FIR|input_process:inst|ptos:inst2|q_temP[3]                                            ; regout           ;
; |CH_FIR|input_process:inst|ptos:inst2|q_temP[4]                                            ; |CH_FIR|input_process:inst|ptos:inst2|q_temP[4]                                            ; regout           ;
; |CH_FIR|input_process:inst|ptos:inst2|q_temP~108                                           ; |CH_FIR|input_process:inst|ptos:inst2|q_temP~108                                           ; combout          ;
; |CH_FIR|input_process:inst|ptos:inst2|q_temP[5]                                            ; |CH_FIR|input_process:inst|ptos:inst2|q_temP[5]                                            ; regout