ch_fir.sim.rpt

来自「基于分布式算法的FPGA实现的FIR滤波器源码」· RPT 代码 · 共 376 行 · 第 1/5 页

; |CH_FIR|LATCH8:inst1|Q_TEMP[10]                                                                         ; |CH_FIR|LATCH8:inst1|Q_TEMP[10]                                                                   ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[9]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[9]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[8]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[8]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[7]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[7]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[6]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[6]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[5]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[5]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[4]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[4]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[3]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[3]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[2]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[2]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[1]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[1]                                                                    ; regout           ;
; |CH_FIR|LATCH8:inst1|Q_TEMP[0]                                                                          ; |CH_FIR|LATCH8:inst1|Q_TEMP[0]                                                                    ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[10]                                                                    ; |CH_FIR|mac:inst2|sa:inst|sa_out[10]                                                              ; regout           ;
; |CH_FIR|controller:inst3|cc:inst|present_state.s3                                                       ; |CH_FIR|controller:inst3|cc:inst|present_state.s3                                                 ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[9]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[9]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[8]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[8]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[7]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[7]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[6]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[6]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[5]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[5]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[4]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[4]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[3]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[3]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[2]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[2]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[1]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[1]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|sa_out[0]                                                                     ; |CH_FIR|mac:inst2|sa:inst|sa_out[0]                                                               ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[9]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[9]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[8]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[8]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[7]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[7]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[6]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[6]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[5]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[5]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[4]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[4]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[3]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[3]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[2]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[2]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[1]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[1]                                                            ; regout           ;
; |CH_FIR|mac:inst2|sa:inst|shift_out[0]                                                                  ; |CH_FIR|mac:inst2|sa:inst|shift_out[0]                                                            ; regout           ;
; |CH_FIR|controller:inst3|cc:inst|present_state.s1                                                       ; |CH_FIR|controller:inst3|cc:inst|present_state.s1                                                 ; regout           ;
; |CH_FIR|controller:inst3|cc:inst|clear~0                                                                ; |CH_FIR|controller:inst3|cc:inst|clear~0                                                          ; combout          ;
; |CH_FIR|controller:inst3|div9:inst1|clk_temp                                                            ; |CH_FIR|controller:inst3|div9:inst1|clk_temp                                                      ; regout           ;
; |CH_FIR|controller:inst3|cc:inst|present_state.s2                                                       ; |CH_FIR|controller:inst3|cc:inst|present_state.s2                                                 ; regout           ;
; |CH_FIR|controller:inst3|cc:inst|next_state.s3~8                                                        ; |CH_FIR|controller:inst3|cc:inst|next_state.s3~8                                                  ; combout          ;
; |CH_FIR|input_process:inst|ptos:inst2|q_temP[0]                                                         ; |CH_FIR|input_process:inst|ptos:inst2|q_temP[0]                                                   ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|do                        ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|do                  ; regout           ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx|S~14                 ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:0:serial_adderx|S~14           ; combout          ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:1:serial_adderx|Cin                  ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:1:serial_adderx|Cin            ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|do                        ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|do                  ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|do                        ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|do                  ; regout           ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:1:serial_adderx|S~14                 ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:1:serial_adderx|S~14           ; combout          ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:2:serial_adderx|Cin                  ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:2:serial_adderx|Cin            ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|do                        ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|do                  ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|do                        ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|do                  ; regout           ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:2:serial_adderx|S~14                 ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:2:serial_adderx|S~14           ; combout          ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:3:serial_adderx|Cin                  ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:3:serial_adderx|Cin            ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|do                        ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|do                  ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|do                        ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|do                  ; regout           ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:3:serial_adderx|S~14                 ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:3:serial_adderx|S~14           ; combout          ;
; |CH_FIR|controller:inst3|cc:inst|Selector0~8                                                            ; |CH_FIR|controller:inst3|cc:inst|Selector0~8                                                      ; combout          ;
; |CH_FIR|controller:inst3|div9:inst1|cnt[3]                                                              ; |CH_FIR|controller:inst3|div9:inst1|cnt[3]                                                        ; regout           ;
; |CH_FIR|controller:inst3|div9:inst1|cnt[0]                                                              ; |CH_FIR|controller:inst3|div9:inst1|cnt[0]                                                        ; regout           ;
; |CH_FIR|controller:inst3|div9:inst1|cnt[1]                                                              ; |CH_FIR|controller:inst3|div9:inst1|cnt[1]                                                        ; regout           ;
; |CH_FIR|controller:inst3|div9:inst1|cnt[2]                                                              ; |CH_FIR|controller:inst3|div9:inst1|cnt[2]                                                        ; regout           ;
; |CH_FIR|controller:inst3|div9:inst1|Equal0~37                                                           ; |CH_FIR|controller:inst3|div9:inst1|Equal0~37                                                     ; combout          ;
; |CH_FIR|controller:inst3|cc:inst|Selector1~8                                                            ; |CH_FIR|controller:inst3|cc:inst|Selector1~8                                                      ; combout          ;
; |CH_FIR|input_process:inst|ptos:inst2|q_temP[1]                                                         ; |CH_FIR|input_process:inst|ptos:inst2|q_temP[1]                                                   ; regout           ;
; |CH_FIR|input_process:inst|ptos:inst2|q_temP~105                                                        ; |CH_FIR|input_process:inst|ptos:inst2|q_temP~105                                                  ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[8]                      ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:6:shift_regx|q[8]                ; regout           ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:1:serial_adderx|Cin~130              ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:1:serial_adderx|Cin~130        ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[8]                      ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:5:shift_regx|q[8]                ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[8]                      ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:0:shift_regx|q[8]                ; regout           ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:2:serial_adderx|Cin~130              ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:2:serial_adderx|Cin~130        ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[8]                      ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:4:shift_regx|q[8]                ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[8]                      ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:1:shift_regx|q[8]                ; regout           ;
; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:3:serial_adderx|Cin~130              ; |CH_FIR|input_process:inst|Serial_adder4:inst|serial_adder:\label1:3:serial_adderx|Cin~130        ; combout          ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[8]                      ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:3:shift_regx|q[8]                ; regout           ;
; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[8]                      ; |CH_FIR|input_process:inst|shiftregister:inst1|shift_reg:\label2:2:shift_regx|q[8]                ; regout           ;
; |CH_FIR|controller:inst3|div9:inst1|cnt~74                                                              ; |CH_FIR|controller:inst3|div9:inst1|cnt~74                                                        ; combout          ;
; |CH_FIR|controller:inst3|div9:inst1|cnt~75                                                              ; |CH_FIR|controller:inst3|div9:inst1|cnt~75                                                        ; combout          ;
; |CH_FIR|controller:inst3|div9:inst1|cnt[1]~76                                                           ; |CH_FIR|controller:inst3|div9:inst1|cnt[1]~76                                                     ; combout          ;
; |CH_FIR|controller:inst3|div9:inst1|cnt[2]~77                                                           ; |CH_FIR|controller:inst3|div9:inst1|cnt[2]~77                                                     ; combout          ;