serial_adder.vhd

来自「基于分布式算法的FPGA实现的FIR滤波器源码」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
entity serial_adder is
Port(A:in std_logic;
B:in std_logic;
clk:in std_logic;
clr:in std_logic;
S:out std_logic);
end serial_adder;
architecture structure of serial_adder is
signal temp1,temp2,Cin,Cout:std_logic;
begin
lablel:Process(clk,clr)
begin
if(clk'event and clk='1') then
if(clr='0')then
Cin<='0';
else Cin<=Cout;
end if;
end if;
end Process;
temp1<=A xor B;
temp2<=temp1 and Cin;
S<=temp1 xor Cin;
Cout<=temp2 or(A and B);
end structure;