📄 counter.rpt
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-- Node name is ':165'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = DFFE( _EQ021, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ021 = _LC1_C4 & !_LC2_C4 & !_LC4_C4
# !_LC1_C4 & _LC2_C4 & !_LC4_C4 & _LC4_C18
# _LC1_C4 & !_LC4_C4 & !_LC4_C18;
-- Node name is ':166'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = DFFE( _EQ022, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ022 = _LC2_C4 & !_LC4_C4 & !_LC4_C18
# !_LC2_C4 & !_LC4_C4 & _LC4_C18;
-- Node name is '~212~1'
-- Equation name is '~212~1', location is LC2_B7, type is buried.
-- synthesized logic cell
!_LC2_B7 = _LC2_B7~NOT;
_LC2_B7~NOT = LCELL( _EQ023);
_EQ023 = _LC1_B7 & !_LC6_B7 & !_LC8_B7;
-- Node name is ':212'
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ024);
_EQ024 = !_LC2_B7 & _LC4_B7 & _LC4_B13;
-- Node name is ':243'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = DFFE( _EQ025, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ025 = _LC2_C18 & !_LC4_C18 & !_LC8_C18
# !_LC2_C18 & !_LC4_C18 & _LC7_B7 & _LC8_C18
# _LC2_C18 & !_LC4_C18 & !_LC7_B7;
-- Node name is ':244'
-- Equation name is '_LC7_C18', type is buried
_LC7_C18 = DFFE( _EQ026, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ026 = !_LC4_C18 & !_LC6_C18 & _LC7_C18
# !_LC4_C18 & _LC6_C18 & _LC7_B7 & !_LC7_C18
# !_LC4_C18 & !_LC7_B7 & _LC7_C18;
-- Node name is ':245'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = DFFE( _EQ027, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ027 = _LC1_C18 & !_LC3_C18 & !_LC4_C18
# !_LC1_C18 & _LC3_C18 & !_LC4_C18 & _LC7_B7
# _LC1_C18 & !_LC4_C18 & !_LC7_B7;
-- Node name is ':246'
-- Equation name is '_LC3_C18', type is buried
_LC3_C18 = DFFE( _EQ028, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ028 = _LC3_C18 & !_LC4_C18 & !_LC7_B7
# !_LC3_C18 & !_LC4_C18 & _LC7_B7;
-- Node name is '~287~1'
-- Equation name is '~287~1', location is LC3_B13, type is buried.
-- synthesized logic cell
!_LC3_B13 = _LC3_B13~NOT;
_LC3_B13~NOT = LCELL( _EQ029);
_EQ029 = _LC1_B13 & !_LC5_B13 & !_LC7_B13;
-- Node name is ':287'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ030);
_EQ030 = _LC2_B13 & _LC3_A16 & !_LC3_B13;
-- Node name is ':326'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = DFFE( _EQ031, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ031 = _LC1_B7 & !_LC5_B7 & !_LC7_B7
# !_LC1_B7 & _LC4_B13 & _LC5_B7 & !_LC7_B7
# _LC1_B7 & !_LC4_B13 & !_LC7_B7;
-- Node name is ':327'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE( _EQ032, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ032 = !_LC3_B7 & _LC6_B7 & !_LC7_B7
# _LC3_B7 & _LC4_B13 & !_LC6_B7 & !_LC7_B7
# !_LC4_B13 & _LC6_B7 & !_LC7_B7;
-- Node name is ':328'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = DFFE( _EQ033, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ033 = !_LC4_B7 & !_LC7_B7 & _LC8_B7
# _LC4_B7 & _LC4_B13 & !_LC7_B7 & !_LC8_B7
# !_LC4_B13 & !_LC7_B7 & _LC8_B7;
-- Node name is ':329'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = DFFE( _EQ034, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ034 = _LC4_B7 & !_LC4_B13 & !_LC7_B7
# !_LC4_B7 & _LC4_B13 & !_LC7_B7;
-- Node name is '~365~1'
-- Equation name is '~365~1', location is LC5_A16, type is buried.
-- synthesized logic cell
!_LC5_A16 = _LC5_A16~NOT;
_LC5_A16~NOT = LCELL( _EQ035);
_EQ035 = !_LC2_A16 & !_LC4_A16 & _LC6_A16;
-- Node name is ':365'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = LCELL( _EQ036);
_EQ036 = _LC1_A16 & _LC2_A17 & !_LC5_A16;
-- Node name is ':412'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE( _EQ037, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ037 = _LC1_B13 & !_LC4_B13 & !_LC8_B13
# !_LC1_B13 & _LC3_A16 & !_LC4_B13 & _LC8_B13
# _LC1_B13 & !_LC3_A16 & !_LC4_B13;
-- Node name is ':413'
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = DFFE( _EQ038, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ038 = !_LC4_B13 & !_LC6_B13 & _LC7_B13
# _LC3_A16 & !_LC4_B13 & _LC6_B13 & !_LC7_B13
# !_LC3_A16 & !_LC4_B13 & _LC7_B13;
-- Node name is ':414'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = DFFE( _EQ039, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ039 = !_LC2_B13 & !_LC4_B13 & _LC5_B13
# _LC2_B13 & _LC3_A16 & !_LC4_B13 & !_LC5_B13
# !_LC3_A16 & !_LC4_B13 & _LC5_B13;
-- Node name is ':415'
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = DFFE( _EQ040, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ040 = _LC2_B13 & !_LC3_A16 & !_LC4_B13
# !_LC2_B13 & _LC3_A16 & !_LC4_B13;
-- Node name is '~446~1'
-- Equation name is '~446~1', location is LC1_A17, type is buried.
-- synthesized logic cell
!_LC1_A17 = _LC1_A17~NOT;
_LC1_A17~NOT = LCELL( _EQ041);
_EQ041 = _LC3_A17 & !_LC6_A17 & !_LC8_A17;
-- Node name is ':446'
-- Equation name is '_LC2_A17', type is buried
_LC2_A17 = LCELL( _EQ042);
_EQ042 = !_LC1_A17 & _LC3_A5 & _LC5_A17;
-- Node name is ':501'
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = DFFE( _EQ043, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ043 = !_LC3_A16 & _LC6_A16 & !_LC8_A16
# _LC2_A17 & !_LC3_A16 & !_LC6_A16 & _LC8_A16
# !_LC2_A17 & !_LC3_A16 & _LC6_A16;
-- Node name is ':502'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = DFFE( _EQ044, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ044 = _LC2_A16 & !_LC3_A16 & !_LC7_A16
# !_LC2_A16 & _LC2_A17 & !_LC3_A16 & _LC7_A16
# _LC2_A16 & !_LC2_A17 & !_LC3_A16;
-- Node name is ':503'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = DFFE( _EQ045, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ045 = !_LC1_A16 & !_LC3_A16 & _LC4_A16
# _LC1_A16 & _LC2_A17 & !_LC3_A16 & !_LC4_A16
# !_LC2_A17 & !_LC3_A16 & _LC4_A16;
-- Node name is ':504'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = DFFE( _EQ046, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ046 = _LC1_A16 & !_LC2_A17 & !_LC3_A16
# !_LC1_A16 & _LC2_A17 & !_LC3_A16;
-- Node name is '~530~1'
-- Equation name is '~530~1', location is LC4_A5, type is buried.
-- synthesized logic cell
!_LC4_A5 = _LC4_A5~NOT;
_LC4_A5~NOT = LCELL( _EQ047);
_EQ047 = !_LC1_A5 & _LC2_A5 & !_LC7_A5;
-- Node name is ':530'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ048);
_EQ048 = !_LC4_A5 & _LC5_A5 & _LC8_A4;
-- Node name is ':593'
-- Equation name is '_LC3_A17', type is buried
_LC3_A17 = DFFE( _EQ049, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ049 = !_LC2_A17 & _LC3_A17 & !_LC7_A17
# !_LC2_A17 & _LC3_A5 & !_LC3_A17 & _LC7_A17
# !_LC2_A17 & !_LC3_A5 & _LC3_A17;
-- Node name is ':594'
-- Equation name is '_LC8_A17', type is buried
_LC8_A17 = DFFE( _EQ050, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ050 = !_LC2_A17 & !_LC4_A17 & _LC8_A17
# !_LC2_A17 & _LC3_A5 & _LC4_A17 & !_LC8_A17
# !_LC2_A17 & !_LC3_A5 & _LC8_A17;
-- Node name is ':595'
-- Equation name is '_LC6_A17', type is buried
_LC6_A17 = DFFE( _EQ051, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ051 = !_LC2_A17 & !_LC5_A17 & _LC6_A17
# !_LC2_A17 & _LC3_A5 & _LC5_A17 & !_LC6_A17
# !_LC2_A17 & !_LC3_A5 & _LC6_A17;
-- Node name is ':596'
-- Equation name is '_LC5_A17', type is buried
_LC5_A17 = DFFE( _EQ052, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ052 = !_LC2_A17 & !_LC3_A5 & _LC5_A17
# !_LC2_A17 & _LC3_A5 & !_LC5_A17;
-- Node name is ':612'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = LCELL( _EQ053);
_EQ053 = _LC1_A4 & !_LC2_A4 & !_LC5_A4 & _LC6_A4;
-- Node name is ':688'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = DFFE( _EQ054, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ054 = _LC2_A5 & !_LC3_A5 & !_LC8_A5
# !_LC2_A5 & !_LC3_A5 & _LC8_A4 & _LC8_A5
# _LC2_A5 & !_LC3_A5 & !_LC8_A4;
-- Node name is ':689'
-- Equation name is '_LC7_A5', type is buried
_LC7_A5 = DFFE( _EQ055, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ055 = !_LC3_A5 & !_LC6_A5 & _LC7_A5
# !_LC3_A5 & _LC6_A5 & !_LC7_A5 & _LC8_A4
# !_LC3_A5 & _LC7_A5 & !_LC8_A4;
-- Node name is ':690'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = DFFE( _EQ056, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ056 = _LC1_A5 & !_LC3_A5 & !_LC5_A5
# !_LC1_A5 & !_LC3_A5 & _LC5_A5 & _LC8_A4
# _LC1_A5 & !_LC3_A5 & !_LC8_A4;
-- Node name is ':691'
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = DFFE( _EQ057, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ057 = !_LC3_A5 & _LC5_A5 & !_LC8_A4
# !_LC3_A5 & !_LC5_A5 & _LC8_A4;
-- Node name is ':774'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = DFFE( _EQ058, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ058 = _LC1_A4 & _LC2_A4 & _LC5_A4 & !_LC6_A4
# !_LC1_A4 & _LC6_A4
# !_LC2_A4 & _LC5_A4 & _LC6_A4
# _LC2_A4 & !_LC5_A4 & _LC6_A4;
-- Node name is ':775'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = DFFE( _EQ059, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ059 = !_LC2_A4 & _LC5_A4
# !_LC1_A4 & _LC5_A4
# _LC1_A4 & _LC2_A4 & !_LC5_A4;
-- Node name is ':776'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = DFFE( _EQ060, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ060 = !_LC1_A4 & _LC2_A4
# _LC1_A4 & !_LC2_A4 & !_LC6_A4
# _LC1_A4 & !_LC2_A4 & _LC5_A4;
-- Node name is ':777'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = DFFE(!_LC1_A4, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
Project Information e:\datacont\counter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 51,474K
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