📄 counter.rpt
字号:
- 1 - C 18 DFFE + 0 3 1 3 :245
- 3 - C 18 DFFE + 0 2 1 4 :246
- 3 - B 13 AND2 s ! 0 3 0 1 ~287~1
- 4 - B 13 AND2 0 3 0 9 :287
- 1 - B 07 DFFE + 0 3 1 1 :326
- 6 - B 07 DFFE + 0 3 1 2 :327
- 8 - B 07 DFFE + 0 3 1 3 :328
- 4 - B 07 DFFE + 0 2 1 4 :329
- 5 - A 16 AND2 s ! 0 3 0 1 ~365~1
- 3 - A 16 AND2 0 3 0 9 :365
- 1 - B 13 DFFE + 0 3 1 1 :412
- 7 - B 13 DFFE + 0 3 1 2 :413
- 5 - B 13 DFFE + 0 3 1 3 :414
- 2 - B 13 DFFE + 0 2 1 4 :415
- 1 - A 17 AND2 s ! 0 3 0 1 ~446~1
- 2 - A 17 AND2 0 3 0 9 :446
- 6 - A 16 DFFE + 0 3 1 1 :501
- 2 - A 16 DFFE + 0 3 1 2 :502
- 4 - A 16 DFFE + 0 3 1 3 :503
- 1 - A 16 DFFE + 0 2 1 4 :504
- 4 - A 05 AND2 s ! 0 3 0 1 ~530~1
- 3 - A 05 AND2 0 3 0 9 :530
- 3 - A 17 DFFE + 0 3 1 1 :593
- 8 - A 17 DFFE + 0 3 1 2 :594
- 6 - A 17 DFFE + 0 3 1 3 :595
- 5 - A 17 DFFE + 0 2 1 4 :596
- 8 - A 04 AND2 0 4 0 5 :612
- 2 - A 05 DFFE + 0 3 1 1 :688
- 7 - A 05 DFFE + 0 3 1 2 :689
- 1 - A 05 DFFE + 0 3 1 3 :690
- 5 - A 05 DFFE + 0 2 1 4 :691
- 6 - A 04 DFFE + 0 3 1 2 :774
- 5 - A 04 DFFE + 0 2 1 3 :775
- 2 - A 04 DFFE + 0 3 1 3 :776
- 1 - A 04 DFFE + 0 0 1 4 :777
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\datacont\counter.rpt
counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 4/ 48( 8%) 5/ 48( 10%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 3/ 96( 3%) 4/ 48( 8%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 3/ 96( 3%) 4/ 48( 8%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\datacont\counter.rpt
counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 clkput
Device-Specific Information: e:\datacont\counter.rpt
counter
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 32 REST
Device-Specific Information: e:\datacont\counter.rpt
counter
** EQUATIONS **
clkput : INPUT;
REST : INPUT;
-- Node name is 'A0'
-- Equation name is 'A0', type is output
A0 = _LC1_A4;
-- Node name is 'A1'
-- Equation name is 'A1', type is output
A1 = _LC2_A4;
-- Node name is 'A2'
-- Equation name is 'A2', type is output
A2 = _LC5_A4;
-- Node name is 'A3'
-- Equation name is 'A3', type is output
A3 = _LC6_A4;
-- Node name is 'B0'
-- Equation name is 'B0', type is output
B0 = _LC5_A5;
-- Node name is 'B1'
-- Equation name is 'B1', type is output
B1 = _LC1_A5;
-- Node name is 'B2'
-- Equation name is 'B2', type is output
B2 = _LC7_A5;
-- Node name is 'B3'
-- Equation name is 'B3', type is output
B3 = _LC2_A5;
-- Node name is 'C0'
-- Equation name is 'C0', type is output
C0 = _LC5_A17;
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = _LC6_A17;
-- Node name is 'C2'
-- Equation name is 'C2', type is output
C2 = _LC8_A17;
-- Node name is 'C3'
-- Equation name is 'C3', type is output
C3 = _LC3_A17;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC1_A16;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC4_A16;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC2_A16;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC6_A16;
-- Node name is 'E0'
-- Equation name is 'E0', type is output
E0 = _LC2_B13;
-- Node name is 'E1'
-- Equation name is 'E1', type is output
E1 = _LC5_B13;
-- Node name is 'E2'
-- Equation name is 'E2', type is output
E2 = _LC7_B13;
-- Node name is 'E3'
-- Equation name is 'E3', type is output
E3 = _LC1_B13;
-- Node name is 'F0'
-- Equation name is 'F0', type is output
F0 = _LC4_B7;
-- Node name is 'F1'
-- Equation name is 'F1', type is output
F1 = _LC8_B7;
-- Node name is 'F2'
-- Equation name is 'F2', type is output
F2 = _LC6_B7;
-- Node name is 'F3'
-- Equation name is 'F3', type is output
F3 = _LC1_B7;
-- Node name is 'G0'
-- Equation name is 'G0', type is output
G0 = _LC3_C18;
-- Node name is 'G1'
-- Equation name is 'G1', type is output
G1 = _LC1_C18;
-- Node name is 'G2'
-- Equation name is 'G2', type is output
G2 = _LC7_C18;
-- Node name is 'G3'
-- Equation name is 'G3', type is output
G3 = _LC2_C18;
-- Node name is 'H0'
-- Equation name is 'H0', type is output
H0 = _LC2_C4;
-- Node name is 'H1'
-- Equation name is 'H1', type is output
H1 = _LC1_C4;
-- Node name is 'H2'
-- Equation name is 'H2', type is output
H2 = _LC5_C4;
-- Node name is 'H3'
-- Equation name is 'H3', type is output
H3 = _LC7_C4;
-- Node name is '|lpm_add_sub:778|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( _EQ001);
_EQ001 = _LC1_C4 & _LC2_C4;
-- Node name is '|lpm_add_sub:778|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = LCELL( _EQ002);
_EQ002 = _LC1_C4 & _LC2_C4 & _LC5_C4;
-- Node name is '|lpm_add_sub:779|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C18', type is buried
_LC6_C18 = LCELL( _EQ003);
_EQ003 = _LC1_C18 & _LC3_C18;
-- Node name is '|lpm_add_sub:779|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = LCELL( _EQ004);
_EQ004 = _LC1_C18 & _LC3_C18 & _LC7_C18;
-- Node name is '|lpm_add_sub:780|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = LCELL( _EQ005);
_EQ005 = _LC4_B7 & _LC8_B7;
-- Node name is '|lpm_add_sub:780|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ006);
_EQ006 = _LC4_B7 & _LC6_B7 & _LC8_B7;
-- Node name is '|lpm_add_sub:781|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ007);
_EQ007 = _LC2_B13 & _LC5_B13;
-- Node name is '|lpm_add_sub:781|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ008);
_EQ008 = _LC2_B13 & _LC5_B13 & _LC7_B13;
-- Node name is '|lpm_add_sub:782|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ009);
_EQ009 = _LC1_A16 & _LC4_A16;
-- Node name is '|lpm_add_sub:782|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = LCELL( _EQ010);
_EQ010 = _LC1_A16 & _LC2_A16 & _LC4_A16;
-- Node name is '|lpm_add_sub:783|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_A17', type is buried
_LC4_A17 = LCELL( _EQ011);
_EQ011 = _LC5_A17 & _LC6_A17;
-- Node name is '|lpm_add_sub:783|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A17', type is buried
_LC7_A17 = LCELL( _EQ012);
_EQ012 = _LC5_A17 & _LC6_A17 & _LC8_A17;
-- Node name is '|lpm_add_sub:784|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ013);
_EQ013 = _LC1_A5 & _LC5_A5;
-- Node name is '|lpm_add_sub:784|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A5', type is buried
_LC8_A5 = LCELL( _EQ014);
_EQ014 = _LC1_A5 & _LC5_A5 & _LC7_A5;
-- Node name is '~89~1'
-- Equation name is '~89~1', location is LC3_C4, type is buried.
-- synthesized logic cell
_LC3_C4 = LCELL( _EQ015);
_EQ015 = !_LC7_C4
# _LC5_C4
# _LC1_C4;
-- Node name is ':89'
-- Equation name is '_LC4_C4', type is buried
!_LC4_C4 = _LC4_C4~NOT;
_LC4_C4~NOT = LCELL( _EQ016);
_EQ016 = !_LC2_C4
# _LC3_C4
# !_LC4_C18;
-- Node name is '~140~1'
-- Equation name is '~140~1', location is LC5_C18, type is buried.
-- synthesized logic cell
!_LC5_C18 = _LC5_C18~NOT;
_LC5_C18~NOT = LCELL( _EQ017);
_EQ017 = !_LC1_C18 & _LC2_C18 & !_LC7_C18;
-- Node name is ':140'
-- Equation name is '_LC4_C18', type is buried
_LC4_C18 = LCELL( _EQ018);
_EQ018 = _LC3_C18 & !_LC5_C18 & _LC7_B7;
-- Node name is ':163'
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = DFFE( _EQ019, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ019 = !_LC4_C4 & _LC7_C4 & !_LC8_C4
# !_LC4_C4 & _LC4_C18 & !_LC7_C4 & _LC8_C4
# !_LC4_C4 & !_LC4_C18 & _LC7_C4;
-- Node name is ':164'
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = DFFE( _EQ020, GLOBAL( clkput), GLOBAL( REST), VCC, VCC);
_EQ020 = !_LC4_C4 & _LC5_C4 & !_LC6_C4
# !_LC4_C4 & _LC4_C18 & !_LC5_C4 & _LC6_C4
# !_LC4_C4 & !_LC4_C18 & _LC5_C4;
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