📄 date.rpt
字号:
- 4 - E 32 AND2 0 2 0 1 |counter:3|lpm_add_sub:781|addcore:adder|:55
- 4 - E 24 AND2 0 3 0 1 |counter:3|lpm_add_sub:781|addcore:adder|:59
- 2 - E 05 AND2 0 2 0 1 |counter:3|lpm_add_sub:782|addcore:adder|:55
- 7 - E 35 AND2 0 3 0 1 |counter:3|lpm_add_sub:782|addcore:adder|:59
- 1 - E 20 AND2 0 2 0 1 |counter:3|lpm_add_sub:783|addcore:adder|:55
- 3 - E 31 AND2 0 3 0 1 |counter:3|lpm_add_sub:783|addcore:adder|:59
- 3 - E 25 AND2 0 2 0 1 |counter:3|lpm_add_sub:784|addcore:adder|:55
- 5 - E 27 AND2 0 3 0 1 |counter:3|lpm_add_sub:784|addcore:adder|:59
- 6 - E 22 OR2 ! 0 4 0 4 |counter:3|:89
- 4 - E 19 OR2 ! 0 4 0 9 |counter:3|:140
- 2 - E 22 DFFE + 0 4 0 3 |counter:3|:163
- 5 - E 22 DFFE + 0 4 0 5 |counter:3|:164
- 8 - E 22 DFFE + 0 4 0 6 |counter:3|:165
- 1 - E 22 DFFE + 0 3 0 7 |counter:3|:166
- 3 - E 26 OR2 ! 0 4 0 9 |counter:3|:212
- 5 - E 19 DFFE + 0 4 0 3 |counter:3|:243
- 2 - E 23 DFFE + 0 4 0 3 |counter:3|:244
- 1 - E 23 DFFE + 0 4 0 4 |counter:3|:245
- 3 - E 23 DFFE + 0 3 0 7 |counter:3|:246
- 2 - E 24 OR2 s 0 2 0 3 |counter:3|~287~1
- 5 - E 24 OR2 ! 0 4 0 9 |counter:3|:287
- 6 - E 26 DFFE + 0 4 0 3 |counter:3|:326
- 2 - E 33 DFFE + 0 4 0 4 |counter:3|:327
- 1 - E 26 DFFE + 0 4 0 5 |counter:3|:328
- 1 - E 33 DFFE + 0 3 0 6 |counter:3|:329
- 2 - E 35 OR2 ! 0 4 0 9 |counter:3|:365
- 6 - E 24 DFFE + 0 4 0 3 |counter:3|:412
- 1 - E 32 DFFE + 0 4 0 3 |counter:3|:413
- 2 - E 32 DFFE + 0 4 0 4 |counter:3|:414
- 8 - E 32 DFFE + 0 3 0 7 |counter:3|:415
- 8 - E 31 OR2 ! 0 4 0 9 |counter:3|:446
- 8 - E 35 DFFE + 0 4 0 3 |counter:3|:501
- 4 - E 35 DFFE + 0 4 0 3 |counter:3|:502
- 1 - E 35 DFFE + 0 4 0 4 |counter:3|:503
- 1 - E 29 DFFE + 0 3 0 7 |counter:3|:504
- 4 - E 27 OR2 ! 0 4 0 9 |counter:3|:530
- 4 - E 31 DFFE + 0 4 0 3 |counter:3|:593
- 2 - E 20 DFFE + 0 4 0 3 |counter:3|:594
- 8 - E 20 DFFE + 0 4 0 4 |counter:3|:595
- 3 - E 20 DFFE + 0 3 0 7 |counter:3|:596
- 2 - E 16 OR2 ! 0 4 0 6 |counter:3|:612
- 6 - E 27 DFFE + 0 4 0 3 |counter:3|:688
- 2 - E 25 DFFE + 0 4 0 4 |counter:3|:689
- 2 - E 27 DFFE + 0 4 0 5 |counter:3|:690
- 1 - E 25 DFFE + 0 3 0 6 |counter:3|:691
- 5 - E 16 DFFE + 0 4 0 2 |counter:3|:774
- 7 - E 16 DFFE + 0 3 0 3 |counter:3|:775
- 1 - E 16 DFFE + 0 3 0 4 |counter:3|:776
- 4 - E 16 DFFE + 0 1 0 5 |counter:3|:777
- 5 - E 30 DFFE + 0 2 1 8 |sel_counter:4|:44
- 1 - E 28 DFFE + 0 1 1 9 |sel_counter:4|:45
- 4 - C 25 DFFE + 0 0 1 10 |sel_counter:4|:46
- 3 - E 28 AND2 0 3 0 4 |sel_counter:4|:47
- 7 - E 30 AND2 0 3 0 4 |sel_counter:4|:56
- 8 - E 30 AND2 0 3 0 4 |sel_counter:4|:65
- 1 - E 30 AND2 0 3 0 4 |sel_counter:4|:74
- 2 - E 30 AND2 0 3 0 4 |sel_counter:4|:83
- 4 - E 30 AND2 0 3 0 4 |sel_counter:4|:93
- 6 - E 30 AND2 0 3 0 4 |sel_counter:4|:103
- 3 - E 30 AND2 0 3 0 4 |sel_counter:4|:113
- 1 - E 21 OR2 0 3 0 1 |sel_counter:4|:127
- 6 - E 36 OR2 0 3 0 1 |sel_counter:4|:128
- 2 - E 21 OR2 0 3 0 1 |sel_counter:4|:129
- 4 - E 21 OR2 0 3 0 1 |sel_counter:4|:130
- 7 - E 19 OR2 0 3 0 1 |sel_counter:4|:135
- 2 - E 36 OR2 0 3 0 1 |sel_counter:4|:136
- 7 - E 23 OR2 0 3 0 1 |sel_counter:4|:137
- 3 - E 36 OR2 0 3 0 1 |sel_counter:4|:138
- 1 - E 19 OR2 0 3 0 1 |sel_counter:4|:143
- 6 - E 33 OR2 0 3 0 1 |sel_counter:4|:144
- 4 - E 23 OR2 0 3 0 1 |sel_counter:4|:145
- 4 - E 36 OR2 0 3 0 1 |sel_counter:4|:146
- 8 - E 24 OR2 0 3 0 1 |sel_counter:4|:151
- 3 - E 33 OR2 0 3 0 1 |sel_counter:4|:152
- 6 - E 32 OR2 0 3 0 1 |sel_counter:4|:153
- 4 - E 29 OR2 0 3 0 1 |sel_counter:4|:154
- 1 - E 24 OR2 0 3 0 1 |sel_counter:4|:159
- 5 - E 34 OR2 0 3 0 1 |sel_counter:4|:160
- 3 - E 32 OR2 0 3 0 1 |sel_counter:4|:161
- 6 - E 29 OR2 0 3 0 1 |sel_counter:4|:162
- 7 - E 31 OR2 0 3 0 1 |sel_counter:4|:167
- 6 - E 25 OR2 0 3 0 1 |sel_counter:4|:168
- 5 - E 20 OR2 0 3 0 1 |sel_counter:4|:169
- 2 - E 29 OR2 0 3 0 1 |sel_counter:4|:170
- 1 - E 31 OR2 0 3 0 1 |sel_counter:4|:175
- 5 - E 25 OR2 0 3 0 1 |sel_counter:4|:176
- 7 - E 20 OR2 0 3 0 1 |sel_counter:4|:177
- 4 - E 34 OR2 0 3 0 1 |sel_counter:4|:178
- 5 - E 28 OR2 0 3 0 9 |sel_counter:4|:183
- 2 - E 28 OR2 0 3 0 9 |sel_counter:4|:184
- 6 - E 20 OR2 0 3 0 8 |sel_counter:4|:185
- 2 - E 34 OR2 0 3 0 9 |sel_counter:4|:186
- 6 - B 17 AND2 s 0 3 0 1 |xianshi:27|~51~1
- 1 - B 09 OR2 0 3 1 0 |xianshi:27|:160
- 1 - B 17 OR2 s 0 4 0 2 |xianshi:27|~182~1
- 5 - B 17 AND2 s 0 3 0 1 |xianshi:27|~182~2
- 2 - B 17 OR2 s 0 4 0 1 |xianshi:27|~182~3
- 4 - B 14 OR2 0 3 1 0 |xianshi:27|:182
- 1 - B 14 OR2 0 2 1 0 |xianshi:27|:204
- 3 - B 17 OR2 0 4 1 1 |xianshi:27|:226
- 4 - B 17 OR2 0 4 1 0 |xianshi:27|:248
- 1 - B 19 OR2 0 4 1 1 |xianshi:27|:270
- 6 - E 21 OR2 0 4 1 0 |xianshi:27|:292
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\datacont\date.rpt
date
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 5/144( 3%) 5/ 72( 6%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 54/144( 37%) 1/ 72( 1%) 42/ 72( 58%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\datacont\date.rpt
date
** CLOCK SIGNALS **
Type Fan-out Name
DFF 64 |clk_1HZ:19|:114
INPUT 32 clkput
INPUT 26 clk24M
INPUT 3 clksel
Device-Specific Information: e:\datacont\date.rpt
date
** CLEAR SIGNALS **
Type Fan-out Name
DFF 64 |clk_1HZ:19|:114
Device-Specific Information: e:\datacont\date.rpt
date
** EQUATIONS **
clkput : INPUT;
clksel : INPUT;
clk24M : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC1_B9;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC4_B14;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC1_B14;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC3_B17;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC4_B17;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC1_B19;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC6_E21;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC4_C25;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC1_E28;
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