buffer.rpt

使用vriloge硬件描述语言设计数字频率计

-- Node name is 'BF73' 
-- Equation name is 'BF73', type is output 
BF73     =  _LC6_A1;

-- Node name is ':71' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = DFFE( A3, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':72' 
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = DFFE( A2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':73' 
-- Equation name is '_LC5_B13', type is buried 
_LC5_B13 = DFFE( A1, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':74' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = DFFE( A0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is '~75~1' 
-- Equation name is '~75~1', location is LC4_A13, type is buried.
-- synthesized logic cell 
_LC4_A13 = LCELL( _EQ001);
  _EQ001 = !G0 & !G1 & !G2 &  _LC2_A1;

-- Node name is '~75~2' 
-- Equation name is '~75~2', location is LC6_A13, type is buried.
-- synthesized logic cell 
_LC6_A13 = LCELL( _EQ002);
  _EQ002 = !F3 & !G3 &  _LC4_A13 &  _LC8_A13;

-- Node name is '~75~3' 
-- Equation name is '~75~3', location is LC8_C11, type is buried.
-- synthesized logic cell 
_LC8_C11 = LCELL( _EQ003);
  _EQ003 = !D0 & !D1 & !D2;

-- Node name is '~75~4' 
-- Equation name is '~75~4', location is LC4_C11, type is buried.
-- synthesized logic cell 
_LC4_C11 = LCELL( _EQ004);
  _EQ004 = !D3 &  _LC6_A13 &  _LC6_C11 &  _LC8_C11;

-- Node name is ':75' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ005);
  _EQ005 = !H0 & !H1 & !H2 & !H3;

-- Node name is '~85~1' 
-- Equation name is '~85~1', location is LC8_A13, type is buried.
-- synthesized logic cell 
_LC8_A13 = LCELL( _EQ006);
  _EQ006 = !F0 & !F1 & !F2;

-- Node name is ':90' 
-- Equation name is '_LC6_C11', type is buried 
_LC6_C11 = LCELL( _EQ007);
  _EQ007 = !E0 & !E1 & !E2 & !E3;

-- Node name is ':100' 
-- Equation name is '_LC3_C21', type is buried 
_LC3_C21 = LCELL( _EQ008);
  _EQ008 = !C0 & !C1 & !C2 & !C3;

-- Node name is ':105' 
-- Equation name is '_LC8_C21', type is buried 
_LC8_C21 = LCELL( _EQ009);
  _EQ009 = !B0 & !B1 & !B2 & !B3;

-- Node name is ':201' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = DFFE( _EQ010, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ010 =  _LC3_C21 &  _LC4_C11 &  _LC8_C21
         #  B3;

-- Node name is ':202' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = DFFE( B2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':203' 
-- Equation name is '_LC6_C21', type is buried 
_LC6_C21 = DFFE( _EQ011, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ011 =  _LC3_C21 &  _LC4_C11 &  _LC8_C21
         #  B1;

-- Node name is ':204' 
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = DFFE( B0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':277' 
-- Equation name is '_LC2_C21', type is buried 
_LC2_C21 = DFFE( _EQ012, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ012 =  _LC3_C21 &  _LC4_C11
         #  C3;

-- Node name is ':278' 
-- Equation name is '_LC2_C4', type is buried 
_LC2_C4  = DFFE( C2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':279' 
-- Equation name is '_LC7_C21', type is buried 
_LC7_C21 = DFFE( _EQ013, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ013 =  _LC3_C21 &  _LC4_C11
         #  C1;

-- Node name is ':280' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = DFFE( C0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':341' 
-- Equation name is '_LC2_C11', type is buried 
_LC2_C11 = DFFE( _EQ014, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ014 =  _LC4_C11
         #  D3;

-- Node name is ':342' 
-- Equation name is '_LC1_C16', type is buried 
_LC1_C16 = DFFE( D2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':343' 
-- Equation name is '_LC7_C11', type is buried 
_LC7_C11 = DFFE( _EQ015, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ015 =  _LC4_C11
         #  D1;

-- Node name is ':344' 
-- Equation name is '_LC5_C11', type is buried 
_LC5_C11 = DFFE( D0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':393' 
-- Equation name is '_LC3_C11', type is buried 
_LC3_C11 = DFFE( _EQ016, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ016 =  _LC6_A13 &  _LC6_C11
         #  E3;

-- Node name is ':394' 
-- Equation name is '_LC3_B21', type is buried 
_LC3_B21 = DFFE( E2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':395' 
-- Equation name is '_LC1_C11', type is buried 
_LC1_C11 = DFFE( _EQ017, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ017 =  _LC6_A13 &  _LC6_C11
         #  E1;

-- Node name is ':396' 
-- Equation name is '_LC8_A14', type is buried 
_LC8_A14 = DFFE( E0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':433' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = DFFE( _EQ018, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ018 =  _LC6_A13
         #  F3;

-- Node name is ':434' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = DFFE( F2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':435' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE( _EQ019, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ019 =  _LC6_A13
         #  F1;

-- Node name is ':436' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = DFFE( F0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':461' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = DFFE( _EQ020, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ020 =  _LC4_A13
         #  G3;

-- Node name is ':462' 
-- Equation name is '_LC5_B6', type is buried 
_LC5_B6  = DFFE( G2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':463' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = DFFE( _EQ021, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ021 = !G3 &  _LC4_A13
         #  G1;

-- Node name is ':464' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = DFFE( G0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':477' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = DFFE( _EQ022, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ022 =  _LC2_A1
         #  H3;

-- Node name is ':478' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = DFFE( H2, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);

-- Node name is ':479' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = DFFE( _EQ023, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);
  _EQ023 =  _LC2_A1
         #  H1;

-- Node name is ':480' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = DFFE( H0, GLOBAL(!clkbuf),  VCC,  VCC,  VCC);



Project Information                                     e:\datacont\buffer.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 53,467K