receiver.tan.qmsg

基于FPGA的uart控制器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "baud_clk register rxcnt16\[2\] register rbuf\[7\]~reg0 204.08 MHz 4.9 ns Internal " "Info: Clock \"baud_clk\" has Internal fmax of 204.08 MHz between source register \"rxcnt16\[2\]\" and destination register \"rbuf\[7\]~reg0\" (period= 4.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.639 ns + Longest register register " "Info: + Longest register to register delay is 4.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxcnt16\[2\] 1 REG LC_X9_Y5_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y5_N2; Fanout = 2; REG Node = 'rxcnt16\[2\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { rxcnt16[2] } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(0.590 ns) 1.751 ns reduce_nor~58 2 COMB LC_X11_Y5_N8 8 " "Info: 2: + IC(1.161 ns) + CELL(0.590 ns) = 1.751 ns; Loc. = LC_X11_Y5_N8; Fanout = 8; COMB Node = 'reduce_nor~58'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.751 ns" { rxcnt16[2] reduce_nor~58 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.292 ns) 2.534 ns rbuf\[0\]~75 3 COMB LC_X11_Y5_N4 8 " "Info: 3: + IC(0.491 ns) + CELL(0.292 ns) = 2.534 ns; Loc. = LC_X11_Y5_N4; Fanout = 8; COMB Node = 'rbuf\[0\]~75'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "0.783 ns" { reduce_nor~58 rbuf[0]~75 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.867 ns) 4.639 ns rbuf\[7\]~reg0 4 REG LC_X11_Y4_N6 1 " "Info: 4: + IC(1.238 ns) + CELL(0.867 ns) = 4.639 ns; Loc. = LC_X11_Y4_N6; Fanout = 1; REG Node = 'rbuf\[7\]~reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.105 ns" { rbuf[0]~75 rbuf[7]~reg0 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.749 ns 37.70 % " "Info: Total cell delay = 1.749 ns ( 37.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.890 ns 62.30 % " "Info: Total interconnect delay = 2.890 ns ( 62.30 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.639 ns" { rxcnt16[2] reduce_nor~58 rbuf[0]~75 rbuf[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.639 ns" { rxcnt16[2] reduce_nor~58 rbuf[0]~75 rbuf[7]~reg0 } { 0.000ns 1.161ns 0.491ns 1.238ns } { 0.000ns 0.590ns 0.292ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 26; CLK Node = 'baud_clk'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { baud_clk } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rbuf\[7\]~reg0 2 REG LC_X11_Y4_N6 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X11_Y4_N6; Fanout = 1; REG Node = 'rbuf\[7\]~reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.261 ns" { baud_clk rbuf[7]~reg0 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rbuf[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rbuf[7]~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"baud_clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 26; CLK Node = 'baud_clk'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { baud_clk } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rxcnt16\[2\] 2 REG LC_X9_Y5_N2 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y5_N2; Fanout = 2; REG Node = 'rxcnt16\[2\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.261 ns" { baud_clk rxcnt16[2] } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rxcnt16[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxcnt16[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rbuf[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rbuf[7]~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rxcnt16[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxcnt16[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.639 ns" { rxcnt16[2] reduce_nor~58 rbuf[0]~75 rbuf[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.639 ns" { rxcnt16[2] reduce_nor~58 rbuf[0]~75 rbuf[7]~reg0 } { 0.000ns 1.161ns 0.491ns 1.238ns } { 0.000ns 0.590ns 0.292ns 0.867ns } } } { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rbuf[7]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rbuf[7]~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rxcnt16[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxcnt16[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "rxcnt16\[2\] rxd baud_clk 7.187 ns register " "Info: tsu for register \"rxcnt16\[2\]\" (data pin = \"rxd\", clock pin = \"baud_clk\") is 7.187 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.880 ns + Longest pin register " "Info: + Longest pin to register delay is 9.880 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rxd 1 PIN PIN_129 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_129; Fanout = 3; PIN Node = 'rxd'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { rxd } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.936 ns) + CELL(0.590 ns) 8.001 ns process0~42 2 COMB LC_X11_Y5_N6 3 " "Info: 2: + IC(5.936 ns) + CELL(0.590 ns) = 8.001 ns; Loc. = LC_X11_Y5_N6; Fanout = 3; COMB Node = 'process0~42'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "6.526 ns" { rxd process0~42 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.141 ns) + CELL(0.738 ns) 9.880 ns rxcnt16\[2\] 3 REG LC_X9_Y5_N2 2 " "Info: 3: + IC(1.141 ns) + CELL(0.738 ns) = 9.880 ns; Loc. = LC_X9_Y5_N2; Fanout = 2; REG Node = 'rxcnt16\[2\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.879 ns" { process0~42 rxcnt16[2] } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.803 ns 28.37 % " "Info: Total cell delay = 2.803 ns ( 28.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.077 ns 71.63 % " "Info: Total interconnect delay = 7.077 ns ( 71.63 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "9.880 ns" { rxd process0~42 rxcnt16[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.880 ns" { rxd rxd~out0 process0~42 rxcnt16[2] } { 0.000ns 0.000ns 5.936ns 1.141ns } { 0.000ns 1.475ns 0.590ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns - Shortest register " "Info: - Shortest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 26; CLK Node = 'baud_clk'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { baud_clk } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rxcnt16\[2\] 2 REG LC_X9_Y5_N2 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X9_Y5_N2; Fanout = 2; REG Node = 'rxcnt16\[2\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.261 ns" { baud_clk rxcnt16[2] } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rxcnt16[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxcnt16[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "9.880 ns" { rxd process0~42 rxcnt16[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.880 ns" { rxd rxd~out0 process0~42 rxcnt16[2] } { 0.000ns 0.000ns 5.936ns 1.141ns } { 0.000ns 1.475ns 0.590ns 0.738ns } } } { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rxcnt16[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxcnt16[2] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "baud_clk rbuf\[6\] rbuf\[6\]~reg0 7.369 ns register " "Info: tco from clock \"baud_clk\" to destination pin \"rbuf\[6\]\" through register \"rbuf\[6\]~reg0\" is 7.369 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"baud_clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 26; CLK Node = 'baud_clk'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { baud_clk } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rbuf\[6\]~reg0 2 REG LC_X12_Y5_N5 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X12_Y5_N5; Fanout = 1; REG Node = 'rbuf\[6\]~reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.261 ns" { baud_clk rbuf[6]~reg0 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rbuf[6]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rbuf[6]~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.415 ns + Longest register pin " "Info: + Longest register to pin delay is 4.415 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rbuf\[6\]~reg0 1 REG LC_X12_Y5_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y5_N5; Fanout = 1; REG Node = 'rbuf\[6\]~reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { rbuf[6]~reg0 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.307 ns) + CELL(2.108 ns) 4.415 ns rbuf\[6\] 2 PIN PIN_55 0 " "Info: 2: + IC(2.307 ns) + CELL(2.108 ns) = 4.415 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'rbuf\[6\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.415 ns" { rbuf[6]~reg0 rbuf[6] } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 47.75 % " "Info: Total cell delay = 2.108 ns ( 47.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.307 ns 52.25 % " "Info: Total interconnect delay = 2.307 ns ( 52.25 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.415 ns" { rbuf[6]~reg0 rbuf[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.415 ns" { rbuf[6]~reg0 rbuf[6] } { 0.000ns 2.307ns } { 0.000ns 2.108ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rbuf[6]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rbuf[6]~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.415 ns" { rbuf[6]~reg0 rbuf[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.415 ns" { rbuf[6]~reg0 rbuf[6] } { 0.000ns 2.307ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "rbuf\[0\]~reg0 rst baud_clk -1.286 ns register " "Info: th for register \"rbuf\[0\]~reg0\" (data pin = \"rst\", clock pin = \"baud_clk\") is -1.286 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 26; CLK Node = 'baud_clk'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { baud_clk } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rbuf\[0\]~reg0 2 REG LC_X11_Y5_N9 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X11_Y5_N9; Fanout = 1; REG Node = 'rbuf\[0\]~reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.261 ns" { baud_clk rbuf[0]~reg0 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rbuf[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rbuf[0]~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.031 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.031 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_16 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 19; PIN Node = 'rst'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { rst } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.114 ns) 2.683 ns rbuf\[0\]~75 2 COMB LC_X11_Y5_N4 8 " "Info: 2: + IC(1.100 ns) + CELL(0.114 ns) = 2.683 ns; Loc. = LC_X11_Y5_N4; Fanout = 8; COMB Node = 'rbuf\[0\]~75'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.214 ns" { rst rbuf[0]~75 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.481 ns) + CELL(0.867 ns) 4.031 ns rbuf\[0\]~reg0 3 REG LC_X11_Y5_N9 1 " "Info: 3: + IC(0.481 ns) + CELL(0.867 ns) = 4.031 ns; Loc. = LC_X11_Y5_N9; Fanout = 1; REG Node = 'rbuf\[0\]~reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.348 ns" { rbuf[0]~75 rbuf[0]~reg0 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.450 ns 60.78 % " "Info: Total cell delay = 2.450 ns ( 60.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.581 ns 39.22 % " "Info: Total interconnect delay = 1.581 ns ( 39.22 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.031 ns" { rst rbuf[0]~75 rbuf[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.031 ns" { rst rst~out0 rbuf[0]~75 rbuf[0]~reg0 } { 0.000ns 0.000ns 1.100ns 0.481ns } { 0.000ns 1.469ns 0.114ns 0.867ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.730 ns" { baud_clk rbuf[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rbuf[0]~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.031 ns" { rst rbuf[0]~75 rbuf[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.031 ns" { rst rst~out0 rbuf[0]~75 rbuf[0]~reg0 } { 0.000ns 0.000ns 1.100ns 0.481ns } { 0.000ns 1.469ns 0.114ns 0.867ns } } }  } 0}