filter.map.qmsg

来自「基于FPGA的uart控制器」· QMSG 代码 · 共 9 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 09 17:21:30 2007 " "Info: Processing started: Sat Jun 09 17:21:30 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off filter -c filter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off filter -c filter" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "filter.vhd 2 1 " "Info: Using design file filter.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 filter-behav " "Info: Found design unit 1: filter-behav" {  } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 filter " "Info: Found entity 1: filter" {  } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "filter " "Info: Elaborating entity \"filter\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 10 -1 0 } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 22 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "6 " "Info: Implemented 6 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 09 17:21:33 2007 " "Info: Processing ended: Sat Jun 09 17:21:33 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}