receiver.fit.qmsg

基于FPGA的uart控制器

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "11 unused 3.30 1 10 0 " "Info: Number of I/O pins in group: 11 (unused VREF, 3.30 VCCIO, 1 input, 10 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 18 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  18 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.057 ns register register " "Info: Estimated most critical path is register to register delay of 4.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxcnt16\[2\] 1 REG LAB_X9_Y5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y5; Fanout = 2; REG Node = 'rxcnt16\[2\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "" { rxcnt16[2] } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.787 ns) + CELL(0.590 ns) 1.377 ns reduce_nor~58 2 COMB LAB_X11_Y5 8 " "Info: 2: + IC(0.787 ns) + CELL(0.590 ns) = 1.377 ns; Loc. = LAB_X11_Y5; Fanout = 8; COMB Node = 'reduce_nor~58'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "1.377 ns" { rxcnt16[2] reduce_nor~58 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.223 ns) + CELL(0.442 ns) 2.042 ns rxd_shift\[0\]~6 3 COMB LAB_X11_Y5 8 " "Info: 3: + IC(0.223 ns) + CELL(0.442 ns) = 2.042 ns; Loc. = LAB_X11_Y5; Fanout = 8; COMB Node = 'rxd_shift\[0\]~6'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "0.665 ns" { reduce_nor~58 rxd_shift[0]~6 } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(0.867 ns) 4.057 ns rxd_shift\[0\] 4 REG LAB_X11_Y4 1 " "Info: 4: + IC(1.148 ns) + CELL(0.867 ns) = 4.057 ns; Loc. = LAB_X11_Y4; Fanout = 1; REG Node = 'rxd_shift\[0\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "2.015 ns" { rxd_shift[0]~6 rxd_shift[0] } "NODE_NAME" } "" } } { "receiver.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/receiver/receiver.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns 46.81 % " "Info: Total cell delay = 1.899 ns ( 46.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.158 ns 53.19 % " "Info: Total interconnect delay = 2.158 ns ( 53.19 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver_cmp.qrpt" Compiler "receiver" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/receiver/db/receiver.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/receiver/" "" "4.057 ns" { rxcnt16[2] reduce_nor~58 rxd_shift[0]~6 rxd_shift[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 11 11:39:57 2007 " "Info: Processing ended: Mon Jun 11 11:39:57 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}