parity_verifier.map.qmsg

基于FPGA的uart控制器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 09 21:39:06 2007 " "Info: Processing started: Sat Jun 09 21:39:06 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off parity_verifier -c parity_verifier " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off parity_verifier -c parity_verifier" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_package.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file uart_package.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_package " "Info: Found design unit 1: uart_package" {  } { { "uart_package.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/uart_package.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 uart_package-body " "Info: Found design unit 2: uart_package-body" {  } { { "uart_package.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/uart_package.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "parity_verifier.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file parity_verifier.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 parity_verifier-parity_verifier " "Info: Found design unit 1: parity_verifier-parity_verifier" {  } { { "parity_verifier.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/parity_verifier.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 parity_verifier " "Info: Found entity 1: parity_verifier" {  } { { "parity_verifier.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/parity_verifier/parity_verifier.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "parity_verifier " "Info: Elaborating entity \"parity_verifier\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "12 " "Info: Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "3 " "Info: Implemented 3 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 09 21:39:09 2007 " "Info: Processing ended: Sat Jun 09 21:39:09 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}