📄 fifo1.tan.qmsg

📁 基于FPGA的uart控制器
💻 QMSG
📖 第 1 页 / 共 3 页
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock memory scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0 memory scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[1\] 196.97 MHz 5.077 ns Internal " "Info: Clock \"clock\" has Internal fmax of 196.97 MHz between source memory \"scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0\" and destination memory \"scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[1\]\" (period= 5.077 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0 1 MEM M4K_X13_Y7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y7; Fanout = 8; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[1\] 2 MEM M4K_X13_Y7 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[1\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.319 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.319 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.015 ns - Smallest " "Info: - Smallest clock skew is -0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.773 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_17 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 77; CLK Node = 'clock'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { clock } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.703 ns) 2.773 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[1\] 2 MEM M4K_X13_Y7 1 " "Info: 2: + IC(0.601 ns) + CELL(0.703 ns) = 2.773 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[1\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "1.304 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns 78.33 % " "Info: Total cell delay = 2.172 ns ( 78.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.67 % " "Info: Total interconnect delay = 0.601 ns ( 21.67 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.773 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.773 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.703ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.788 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_17 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 77; CLK Node = 'clock'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { clock } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.718 ns) 2.788 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0 2 MEM M4K_X13_Y7 8 " "Info: 2: + IC(0.601 ns) + CELL(0.718 ns) = 2.788 ns; Loc. = M4K_X13_Y7; Fanout = 8; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|ram_block1a0~portb_address_reg0'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "1.319 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.187 ns 78.44 % " "Info: Total cell delay = 2.187 ns ( 78.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.56 % " "Info: Total interconnect delay = 0.601 ns ( 21.56 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.788 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.788 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.718ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.773 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.773 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.703ns } } } { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.788 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.788 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.718ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 42 2 0 } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.319 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.773 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.773 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[1] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.703ns } } } { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.788 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.788 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.718ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|empty_dff rdreq clock 8.138 ns register " "Info: tsu for register \"scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|empty_dff\" (data pin = \"rdreq\", clock pin = \"clock\") is 8.138 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.882 ns + Longest pin register " "Info: + Longest pin to register delay is 10.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rdreq 1 PIN PIN_91 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_91; Fanout = 19; PIN Node = 'rdreq'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { rdreq } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.754 ns) + CELL(0.114 ns) 7.337 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|valid_rreq 2 COMB LC_X15_Y7_N8 13 " "Info: 2: + IC(5.754 ns) + CELL(0.114 ns) = 7.337 ns; Loc. = LC_X15_Y7_N8; Fanout = 13; COMB Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|valid_rreq'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "5.868 ns" { rdreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|valid_rreq } "NODE_NAME" } "" } } { "db/a_dpfifo_3rr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/a_dpfifo_3rr.tdf" 74 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.225 ns) + CELL(0.590 ns) 9.152 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|_~66 3 COMB LC_X15_Y8_N9 2 " "Info: 3: + IC(1.225 ns) + CELL(0.590 ns) = 9.152 ns; Loc. = LC_X15_Y8_N9; Fanout = 2; COMB Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|_~66'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "1.815 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|_~66 } "NODE_NAME" } "" } } { "db/scfifo_skr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/scfifo_skr.tdf" 37 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.252 ns) + CELL(0.478 ns) 10.882 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|empty_dff 4 REG LC_X15_Y7_N5 20 " "Info: 4: + IC(1.252 ns) + CELL(0.478 ns) = 10.882 ns; Loc. = LC_X15_Y7_N5; Fanout = 20; REG Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|empty_dff'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "1.730 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|_~66 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } "NODE_NAME" } "" } } { "db/a_dpfifo_3rr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/a_dpfifo_3rr.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.651 ns 24.36 % " "Info: Total cell delay = 2.651 ns ( 24.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.231 ns 75.64 % " "Info: Total interconnect delay = 8.231 ns ( 75.64 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "10.882 ns" { rdreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|_~66 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.882 ns" { rdreq rdreq~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|_~66 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } { 0.000ns 0.000ns 5.754ns 1.225ns 1.252ns } { 0.000ns 1.469ns 0.114ns 0.590ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/a_dpfifo_3rr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/a_dpfifo_3rr.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.781 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_17 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 77; CLK Node = 'clock'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { clock } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|empty_dff 2 REG LC_X15_Y7_N5 20 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X15_Y7_N5; Fanout = 20; REG Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|empty_dff'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "1.312 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } "NODE_NAME" } "" } } { "db/a_dpfifo_3rr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/a_dpfifo_3rr.tdf" 45 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.39 % " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.61 % " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.781 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.781 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "10.882 ns" { rdreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|_~66 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.882 ns" { rdreq rdreq~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|valid_rreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|_~66 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } { 0.000ns 0.000ns 5.754ns 1.225ns 1.252ns } { 0.000ns 1.469ns 0.114ns 0.590ns 0.478ns } } } { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.781 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.781 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|empty_dff } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[3\] scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[3\] 8.073 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[3\]\" through memory \"scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[3\]\" is 8.073 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.773 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_17 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 77; CLK Node = 'clock'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { clock } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.703 ns) 2.773 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[3\] 2 MEM M4K_X13_Y7 1 " "Info: 2: + IC(0.601 ns) + CELL(0.703 ns) = 2.773 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[3\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "1.304 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.172 ns 78.33 % " "Info: Total cell delay = 2.172 ns ( 78.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.67 % " "Info: Total interconnect delay = 0.601 ns ( 21.67 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.773 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.773 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.703ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.650 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[3\] 1 MEM M4K_X13_Y7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y7; Fanout = 1; MEM Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|altsyncram_vf31:FIFOram\|q_b\[3\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] } "NODE_NAME" } "" } } { "db/altsyncram_vf31.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/altsyncram_vf31.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.438 ns) + CELL(2.108 ns) 4.650 ns q\[3\] 2 PIN PIN_120 0 " "Info: 2: + IC(2.438 ns) + CELL(2.108 ns) = 4.650 ns; Loc. = PIN_120; Fanout = 0; PIN Node = 'q\[3\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.546 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] q[3] } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 47 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns 47.57 % " "Info: Total cell delay = 2.212 ns ( 47.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.438 ns 52.43 % " "Info: Total interconnect delay = 2.438 ns ( 52.43 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.650 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.650 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] q[3] } { 0.000ns 2.438ns } { 0.104ns 2.108ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.773 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.773 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.703ns } } } { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "4.650 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.650 ns" { scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|altsyncram_vf31:FIFOram|q_b[3] q[3] } { 0.000ns 2.438ns } { 0.104ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|low_addressa\[5\] rdreq clock -4.696 ns register " "Info: th for register \"scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|low_addressa\[5\]\" (data pin = \"rdreq\", clock pin = \"clock\") is -4.696 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.781 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_17 77 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 77; CLK Node = 'clock'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { clock } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 45 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|low_addressa\[5\] 2 REG LC_X17_Y7_N4 2 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X17_Y7_N4; Fanout = 2; REG Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|low_addressa\[5\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "1.312 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } "NODE_NAME" } "" } } { "db/a_dpfifo_3rr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/a_dpfifo_3rr.tdf" 47 14 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.39 % " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.61 % " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.781 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.781 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "db/a_dpfifo_3rr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/a_dpfifo_3rr.tdf" 47 14 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.492 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rdreq 1 PIN PIN_91 19 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_91; Fanout = 19; PIN Node = 'rdreq'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "" { rdreq } "NODE_NAME" } "" } } { "fifo1.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/fifo1.vhd" 44 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.714 ns) + CELL(0.309 ns) 7.492 ns scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|low_addressa\[5\] 2 REG LC_X17_Y7_N4 2 " "Info: 2: + IC(5.714 ns) + CELL(0.309 ns) = 7.492 ns; Loc. = LC_X17_Y7_N4; Fanout = 2; REG Node = 'scfifo:scfifo_component\|scfifo_skr:auto_generated\|a_dpfifo_3rr:dpfifo\|low_addressa\[5\]'" {  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "6.023 ns" { rdreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } "NODE_NAME" } "" } } { "db/a_dpfifo_3rr.tdf" "" { Text "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/a_dpfifo_3rr.tdf" 47 14 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 23.73 % " "Info: Total cell delay = 1.778 ns ( 23.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.714 ns 76.27 % " "Info: Total interconnect delay = 5.714 ns ( 76.27 % )" {  } {  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "7.492 ns" { rdreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.492 ns" { rdreq rdreq~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}  } { { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "2.781 ns" { clock scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.781 ns" { clock clock~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1_cmp.qrpt" Compiler "fifo1" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/fifo1/db/fifo1.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/fifo1/" "" "7.492 ns" { rdreq scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.492 ns" { rdreq rdreq~out0 scfifo:scfifo_component|scfifo_skr:auto_generated|a_dpfifo_3rr:dpfifo|low_addressa[5] } { 0.000ns 0.000ns 5.714ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}
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