uart_testb.map.qmsg

基于FPGA的uart控制器

{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led6\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led6\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led6\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led6\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led6\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led6\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led5\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led5\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led5\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led5\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led5\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led5\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led5\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led5\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led4\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led4\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led4\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led4\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led4\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led4\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led4\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led4\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led3\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led3\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led3\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led3\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led3\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led3\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led3\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led3\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led2\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led2\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led2\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led2\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led2\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led2\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led2\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led2\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led1\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led1\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led1\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led1\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led1\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led1\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led1\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led1\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "uart_test.vhd(154) " "Error (10822): HDL error at uart_test.vhd(154): couldn't implement registers for assignments on this clock edge" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 154 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0}
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "uart_test:inst1 " "Error: Can't elaborate user hierarchy \"uart_test:inst1\"" {  } { { "uart_testb.bdf" "inst1" { Schematic "L:/uart/VHDLoo/uart_test/uart_testb.bdf" { { 168 536 728 456 "inst1" "" } } } }  } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 27 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 27 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "132 " "Info: Allocated 132 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 21 19:55:59 2008 " "Error: Processing ended: Fri Mar 21 19:55:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}