uart_testb.map.qmsg

基于FPGA的uart控制器

{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "clock uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"clock\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "fifo_sel uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"fifo_sel\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "fifo_wr uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"fifo_wr\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "fifo_rd uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"fifo_rd\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "fifo_exit uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"fifo_exit\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "fifo_exit uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"fifo_exit\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "fifo_rd uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"fifo_rd\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "fifo_wr uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"fifo_wr\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "fifo_sel uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"fifo_sel\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "clock uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"clock\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[4\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[4\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[5\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[5\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[6\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[6\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "send_buf\[7\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"send_buf\[7\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "s_cmd_rst uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"s_cmd_rst\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led8\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led8\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led8\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led8\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led8\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led8\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led8\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led8\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led7\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led7\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led7\[1\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led7\[1\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led7\[2\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led7\[2\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led7\[3\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led7\[3\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "led6\[0\] uart_test.vhd(101) " "Info (10041): Verilog HDL or VHDL info at uart_test.vhd(101): inferred latch for \"led6\[0\]\"" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}