uart_testb.map.qmsg

基于FPGA的uart控制器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 21 19:55:56 2008 " "Info: Processing started: Fri Mar 21 19:55:56 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_testb -c uart_testb " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_testb -c uart_testb" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_testb.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_testb.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 uart_testb " "Info: Found entity 1: uart_testb" {  } { { "uart_testb.bdf" "" { Schematic "L:/uart/VHDLoo/uart_test/uart_testb.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart_testb " "Info: Elaborating entity \"uart_testb\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "uart_test.vhd 2 1 " "Warning: Using design file uart_test.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_test-bhv " "Info: Found design unit 1: uart_test-bhv" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 32 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_test " "Info: Found entity 1: uart_test" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_test uart_test:inst1 " "Info: Elaborating entity \"uart_test\" for hierarchy \"uart_test:inst1\"" {  } { { "uart_testb.bdf" "inst1" { Schematic "L:/uart/VHDLoo/uart_test/uart_testb.bdf" { { 168 536 728 456 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "baud_index uart_test.vhd(68) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(68): object \"baud_index\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 68 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "mode_sel uart_test.vhd(72) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(72): object \"mode_sel\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 72 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "h_index uart_test.vhd(74) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(74): object \"h_index\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 74 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "l_index uart_test.vhd(75) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(75): object \"l_index\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 75 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "send_buf_l uart_test.vhd(77) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(77): object \"send_buf_l\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 77 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "send_buf_h uart_test.vhd(77) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(77): object \"send_buf_h\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 77 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "fifo_con1 uart_test.vhd(78) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(78): object \"fifo_con1\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 78 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "fifo_con2 uart_test.vhd(78) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(78): object \"fifo_con2\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 78 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "fifo_con3 uart_test.vhd(78) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(78): object \"fifo_con3\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 78 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "fifo_ful uart_test.vhd(79) " "Warning (10541): VHDL Signal Declaration warning at uart_test.vhd(79): used implicit default value for signal \"fifo_ful\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 79 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "fifo_empty uart_test.vhd(79) " "Warning (10541): VHDL Signal Declaration warning at uart_test.vhd(79): used implicit default value for signal \"fifo_empty\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 79 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "data uart_test.vhd(82) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(82): object \"data\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 82 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "wrreq uart_test.vhd(84) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(84): object \"wrreq\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 84 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "rdreq uart_test.vhd(84) " "Warning (10036): Verilog HDL or VHDL warning at uart_test.vhd(84): object \"rdreq\" assigned a value but never read" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 84 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led3 uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"led3\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led4 uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"led4\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led5 uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"led5\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led6 uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"led6\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led7 uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"led7\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "led8 uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"led8\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "s_cmd_rst uart_test.vhd(101) " "Warning (10631): VHDL Process Statement warning at uart_test.vhd(101): inferring latch(es) for signal or variable \"s_cmd_rst\", which holds its previous value in one or more paths through the process" {  } { { "uart_test.vhd" "" { Text "L:/uart/VHDLoo/uart_test/uart_test.vhd" 101 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}