📄 filter.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "baud_clk register register rxd_sync~reg0 rxd_sync~reg0 275.03 MHz Internal " "Info: Clock \"baud_clk\" Internal fmax is restricted to 275.03 MHz between source register \"rxd_sync~reg0\" and destination register \"rxd_sync~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.260 ns + Longest register register " "Info: + Longest register to register delay is 1.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd_sync~reg0 1 REG LC_X2_Y1_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.738 ns) 1.260 ns rxd_sync~reg0 2 REG LC_X2_Y1_N2 2 " "Info: 2: + IC(0.522 ns) + CELL(0.738 ns) = 1.260 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.260 ns" { rxd_sync~reg0 rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 58.57 % " "Info: Total cell delay = 0.738 ns ( 58.57 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.522 ns 41.43 % " "Info: Total interconnect delay = 0.522 ns ( 41.43 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.260 ns" { rxd_sync~reg0 rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.260 ns" { rxd_sync~reg0 rxd_sync~reg0 } { 0.000ns 0.522ns } { 0.000ns 0.738ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'baud_clk'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { baud_clk } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rxd_sync~reg0 2 REG LC_X2_Y1_N2 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.261 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"baud_clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'baud_clk'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { baud_clk } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rxd_sync~reg0 2 REG LC_X2_Y1_N2 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.261 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.260 ns" { rxd_sync~reg0 rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.260 ns" { rxd_sync~reg0 rxd_sync~reg0 } { 0.000ns 0.522ns } { 0.000ns 0.738ns } } } { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { rxd_sync~reg0 } { } { } } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "samples\[0\] rxd baud_clk 4.308 ns register " "Info: tsu for register \"samples\[0\]\" (data pin = \"rxd\", clock pin = \"baud_clk\") is 4.308 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.001 ns + Longest pin register " "Info: + Longest pin to register delay is 7.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rxd 1 PIN PIN_38 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 2; PIN Node = 'rxd'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { rxd } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.048 ns) + CELL(0.478 ns) 7.001 ns samples\[0\] 2 REG LC_X2_Y1_N4 1 " "Info: 2: + IC(5.048 ns) + CELL(0.478 ns) = 7.001 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; REG Node = 'samples\[0\]'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "5.526 ns" { rxd samples[0] } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns 27.90 % " "Info: Total cell delay = 1.953 ns ( 27.90 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.048 ns 72.10 % " "Info: Total interconnect delay = 5.048 ns ( 72.10 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "7.001 ns" { rxd samples[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.001 ns" { rxd rxd~out0 samples[0] } { 0.000ns 0.000ns 5.048ns } { 0.000ns 1.475ns 0.478ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns - Shortest register " "Info: - Shortest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'baud_clk'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { baud_clk } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns samples\[0\] 2 REG LC_X2_Y1_N4 1 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y1_N4; Fanout = 1; REG Node = 'samples\[0\]'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.261 ns" { baud_clk samples[0] } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk samples[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 samples[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "7.001 ns" { rxd samples[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.001 ns" { rxd rxd~out0 samples[0] } { 0.000ns 0.000ns 5.048ns } { 0.000ns 1.475ns 0.478ns } } } { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk samples[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 samples[0] } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "baud_clk rxd_sync rxd_sync~reg0 6.483 ns register " "Info: tco from clock \"baud_clk\" to destination pin \"rxd_sync\" through register \"rxd_sync~reg0\" is 6.483 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"baud_clk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'baud_clk'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { baud_clk } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rxd_sync~reg0 2 REG LC_X2_Y1_N2 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.261 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.529 ns + Longest register pin " "Info: + Longest register to pin delay is 3.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd_sync~reg0 1 REG LC_X2_Y1_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.405 ns) + CELL(2.124 ns) 3.529 ns rxd_sync 2 PIN PIN_35 0 " "Info: 2: + IC(1.405 ns) + CELL(2.124 ns) = 3.529 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'rxd_sync'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "3.529 ns" { rxd_sync~reg0 rxd_sync } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 60.19 % " "Info: Total cell delay = 2.124 ns ( 60.19 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.405 ns 39.81 % " "Info: Total interconnect delay = 1.405 ns ( 39.81 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "3.529 ns" { rxd_sync~reg0 rxd_sync } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.529 ns" { rxd_sync~reg0 rxd_sync } { 0.000ns 1.405ns } { 0.000ns 2.124ns } } } } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "3.529 ns" { rxd_sync~reg0 rxd_sync } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.529 ns" { rxd_sync~reg0 rxd_sync } { 0.000ns 1.405ns } { 0.000ns 2.124ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "rxd_sync~reg0 rxd baud_clk -4.255 ns register " "Info: th for register \"rxd_sync~reg0\" (data pin = \"rxd\", clock pin = \"baud_clk\") is -4.255 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "baud_clk destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"baud_clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns baud_clk 1 CLK PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'baud_clk'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { baud_clk } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns rxd_sync~reg0 2 REG LC_X2_Y1_N2 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "1.261 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rxd 1 PIN PIN_38 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_38; Fanout = 2; PIN Node = 'rxd'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "" { rxd } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.047 ns) + CELL(0.478 ns) 7.000 ns rxd_sync~reg0 2 REG LC_X2_Y1_N2 2 " "Info: 2: + IC(5.047 ns) + CELL(0.478 ns) = 7.000 ns; Loc. = LC_X2_Y1_N2; Fanout = 2; REG Node = 'rxd_sync~reg0'" { } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "5.525 ns" { rxd rxd_sync~reg0 } "NODE_NAME" } "" } } { "filter.vhd" "" { Text "E:/毕业设计勿删/zhangguang/linshi/filter/filter.vhd" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns 27.90 % " "Info: Total cell delay = 1.953 ns ( 27.90 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.047 ns 72.10 % " "Info: Total interconnect delay = 5.047 ns ( 72.10 % )" { } { } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "7.000 ns" { rxd rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.000 ns" { rxd rxd~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 5.047ns } { 0.000ns 1.475ns 0.478ns } } } } 0} } { { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "2.730 ns" { baud_clk rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { baud_clk baud_clk~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" "" { Report "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter_cmp.qrpt" Compiler "filter" "UNKNOWN" "V1" "E:/毕业设计勿删/zhangguang/linshi/filter/db/filter.quartus_db" { Floorplan "E:/毕业设计勿删/zhangguang/linshi/filter/" "" "7.000 ns" { rxd rxd_sync~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.000 ns" { rxd rxd~out0 rxd_sync~reg0 } { 0.000ns 0.000ns 5.047ns } { 0.000ns 1.475ns 0.478ns } } } } 0}
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