signal.tan.rpt

通信基带信号发生器的设计

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+--------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Type                                                   ; Slack     ; Required Time                    ; Actual Time                                    ; From                                                                     ; To                                                                                                                                                              ; From Clock                              ; To Clock                                ; Failed Paths ;
+--------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Worst-case tsu                                         ; N/A       ; None                             ; 1.826 ns                                       ; EN                                                                       ; PARALLEL:inst6|TEMP2[7]                                                                                                                                         ; --                                      ; TXD                                     ; 0            ;
; Worst-case tco                                         ; N/A       ; None                             ; 24.792 ns                                      ; NCO_AM:inst11|NCO_AM_st:NCO_AM_st_inst|asj_nco_mob_rw:ux122|data_out[1]  ; OUT[8]                                                                                                                                                          ; CLK_IN                                  ; --                                      ; 0            ;
; Worst-case th                                          ; N/A       ; None                             ; 0.131 ns                                       ; MCU_IN[1]                                                                ; PARALLEL:inst6|TEMP3[1]                                                                                                                                         ; --                                      ; TXD                                     ; 0            ;
; Clock Setup: 'PLL:inst4|altpll:altpll_component|_clk0' ; -1.095 ns ; 200.00 MHz ( period = 5.000 ns ) ; N/A                                            ; STATUSCONTROL:inst|EN_FM                                                 ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 ; CLK_IN                                  ; PLL:inst4|altpll:altpll_component|_clk0 ; 1729         ;
; Clock Setup: 'CLK_IN'                                  ; -0.277 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A                                            ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_mob_rw:ux122|data_out[19] ; STATUSCONTROL:inst|FRE7[19]                                                                                                                                     ; PLL:inst4|altpll:altpll_component|_clk0 ; CLK_IN                                  ; 7            ;
; Clock Setup: 'TXD'                                     ; N/A       ; None                             ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; PARALLEL:inst6|TEMP1[6]                                                  ; PARALLEL:inst6|TEMP0[6]                                                                                                                                         ; TXD                                     ; TXD                                     ; 0            ;
; Clock Hold: 'PLL:inst4|altpll:altpll_component|_clk0'  ; 0.859 ns  ; 200.00 MHz ( period = 5.000 ns ) ; N/A                                            ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_dxx:ux002|dxxpdo[7]           ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_gal:ux009|rom_add[2]                                                                                                 ; PLL:inst4|altpll:altpll_component|_clk0 ; PLL:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'CLK_IN'                                   ; 0.861 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                                            ; xulie:inst12|u1                                                          ; xulie:inst12|u2                                                                                                                                                 ; CLK_IN                                  ; CLK_IN                                  ; 0            ;
; Total number of failed paths                           ;           ;                                  ;                                                ;                                                                          ;                                                                                                                                                                 ;                                         ;                                         ; 1736         ;
+--------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                          ;