signal.tan.rpt

来自「通信基带信号发生器的设计」· RPT 代码 · 共 220 行 · 第 1/5 页

+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                         ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; PLL:inst4|altpll:altpll_component|_clk0 ;                    ; PLL output ; 200.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK_IN   ; 4                     ; 1                   ; -1.885 ns ;              ;
; PLL:inst4|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK_IN   ; 2                     ; 1                   ; -1.885 ns ;              ;
; CLK_IN                                  ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; EN                                      ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; TXD                                     ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLL:inst4|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                        ; To                                                                                                                                                              ; From Clock ; To Clock                                ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg9 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg8 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg7 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg6 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg5 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg4 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg3 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg2 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg1 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|ram_block1a22~porta_address_reg0 ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.312 ns                  ; 3.407 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|q_a[21]                          ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.298 ns                  ; 3.393 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|q_a[18]                          ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.298 ns                  ; 3.393 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|q_a[17]                          ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.298 ns                  ; 3.393 ns                ;
; -1.095 ns                               ; None                                                ; STATUSCONTROL:inst|EN_FM    ; NCO_FM:inst31|NCO_FM_st:NCO_FM_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_kq81:auto_generated|q_a[22]                          ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.298 ns                  ; 3.393 ns                ;
; -1.092 ns                               ; None                                                ; STATUSCONTROL:inst|FRE5[1]  ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_fxx:ux003|lpm_add_sub:acc|alt_stratix_add_sub:stratix_adder|result[31]                                                     ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.264 ns                  ; 3.356 ns                ;
; -1.075 ns                               ; None                                                ; STATUSCONTROL:inst|FRE7[0]  ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_fxx:ux003|lpm_add_sub:acc|alt_stratix_add_sub:stratix_adder|result[31]                                                     ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.264 ns                  ; 3.339 ns                ;
; -1.074 ns                               ; None                                                ; STATUSCONTROL:inst|FRE7[3]  ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_fxx:ux003|lpm_add_sub:acc|alt_stratix_add_sub:stratix_adder|result[31]                                                     ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.264 ns                  ; 3.338 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg9            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg8            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg7            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg6            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg5            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg4            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg3            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg2            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg1            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|ram_block1a8~porta_address_reg0            ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.252 ns                  ; 3.317 ns                ;
; -1.065 ns                               ; None                                                ; STATUSCONTROL:inst|EN_SIN   ; NCO:inst2|NCO_st:NCO_st_inst|asj_nco_as_m_cen:ux0120|altsyncram:altsyncram_component0|altsyncram_tg81:auto_generated|q_a[1]                                     ; CLK_IN     ; PLL:inst4|altpll:altpll_component|_clk0 ; 3.115 ns                    ; 2.238 ns                  ; 3.303 ns                ;