qpsktiao.tan.qmsg

用VHDL语言实现QPSK调制功能和解调功能,

{ "Info" "ITDB_TH_RESULT" "seri_2:inst4\|xx\[0\] x clk -0.856 ns register " "Info: th for register \"seri_2:inst4\|xx\[0\]\" (data pin = \"x\", clock pin = \"clk\") is -0.856 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.754 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.787 ns) 2.599 ns fenpin:inst2\|count\[2\] 3 REG LCFF_X27_Y6_N25 3 " "Info: 3: + IC(0.701 ns) + CELL(0.787 ns) = 2.599 ns; Loc. = LCFF_X27_Y6_N25; Fanout = 3; REG Node = 'fenpin:inst2\|count\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.488 ns" { clk~clkctrl fenpin:inst2|count[2] } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/fenpin.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.886 ns) + CELL(0.000 ns) 3.485 ns fenpin:inst2\|count\[2\]~clkctrl 4 COMB CLKCTRL_G4 7 " "Info: 4: + IC(0.886 ns) + CELL(0.000 ns) = 3.485 ns; Loc. = CLKCTRL_G4; Fanout = 7; COMB Node = 'fenpin:inst2\|count\[2\]~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.886 ns" { fenpin:inst2|count[2] fenpin:inst2|count[2]~clkctrl } "NODE_NAME" } } { "fenpin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/fenpin.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.537 ns) 4.754 ns seri_2:inst4\|xx\[0\] 5 REG LCFF_X21_Y13_N7 2 " "Info: 5: + IC(0.732 ns) + CELL(0.537 ns) = 4.754 ns; Loc. = LCFF_X21_Y13_N7; Fanout = 2; REG Node = 'seri_2:inst4\|xx\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.269 ns" { fenpin:inst2|count[2]~clkctrl seri_2:inst4|xx[0] } "NODE_NAME" } } { "seri_2.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/seri_2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 48.65 % ) " "Info: Total cell delay = 2.313 ns ( 48.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.441 ns ( 51.35 % ) " "Info: Total interconnect delay = 2.441 ns ( 51.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.754 ns" { clk clk~clkctrl fenpin:inst2|count[2] fenpin:inst2|count[2]~clkctrl seri_2:inst4|xx[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.754 ns" { clk clk~combout clk~clkctrl fenpin:inst2|count[2] fenpin:inst2|count[2]~clkctrl seri_2:inst4|xx[0] } { 0.000ns 0.000ns 0.122ns 0.701ns 0.886ns 0.732ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "seri_2.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/seri_2.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.876 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.876 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns x 1 PIN PIN_118 2 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_118; Fanout = 2; PIN Node = 'x'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 400 -176 -8 416 "x" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.802 ns) + CELL(0.150 ns) 5.792 ns seri_2:inst4\|xx\[0\]~161 2 COMB LCCOMB_X21_Y13_N6 1 " "Info: 2: + IC(4.802 ns) + CELL(0.150 ns) = 5.792 ns; Loc. = LCCOMB_X21_Y13_N6; Fanout = 1; COMB Node = 'seri_2:inst4\|xx\[0\]~161'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.952 ns" { x seri_2:inst4|xx[0]~161 } "NODE_NAME" } } { "seri_2.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/seri_2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.876 ns seri_2:inst4\|xx\[0\] 3 REG LCFF_X21_Y13_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.876 ns; Loc. = LCFF_X21_Y13_N7; Fanout = 2; REG Node = 'seri_2:inst4\|xx\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { seri_2:inst4|xx[0]~161 seri_2:inst4|xx[0] } "NODE_NAME" } } { "seri_2.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/seri_2.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.074 ns ( 18.28 % ) " "Info: Total cell delay = 1.074 ns ( 18.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.802 ns ( 81.72 % ) " "Info: Total interconnect delay = 4.802 ns ( 81.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.876 ns" { x seri_2:inst4|xx[0]~161 seri_2:inst4|xx[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.876 ns" { x x~combout seri_2:inst4|xx[0]~161 seri_2:inst4|xx[0] } { 0.000ns 0.000ns 4.802ns 0.000ns } { 0.000ns 0.840ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.754 ns" { clk clk~clkctrl fenpin:inst2|count[2] fenpin:inst2|count[2]~clkctrl seri_2:inst4|xx[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.754 ns" { clk clk~combout clk~clkctrl fenpin:inst2|count[2] fenpin:inst2|count[2]~clkctrl seri_2:inst4|xx[0] } { 0.000ns 0.000ns 0.122ns 0.701ns 0.886ns 0.732ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.876 ns" { x seri_2:inst4|xx[0]~161 seri_2:inst4|xx[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.876 ns" { x x~combout seri_2:inst4|xx[0]~161 seri_2:inst4|xx[0] } { 0.000ns 0.000ns 4.802ns 0.000ns } { 0.000ns 0.840ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 09 10:39:16 2008 " "Info: Processing ended: Fri May 09 10:39:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}