qpsktiao.tan.qmsg

用VHDL语言实现QPSK调制功能和解调功能,

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fenpin:inst2\|count\[2\] " "Info: Detected ripple clock \"fenpin:inst2\|count\[2\]\" as buffer" {  } { { "fenpin.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/fenpin.vhd" 22 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fenpin:inst2\|count\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst\|clk_temp " "Info: Detected ripple clock \"clk_div:inst\|clk_temp\" as buffer" {  } { { "clk_div.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/clk_div.vhd" 18 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_div:inst\|clk_temp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register select4_1:inst3\|q\[6\] register counter8:inst1\|q\[6\]~reg0 317.36 MHz 3.151 ns Internal " "Info: Clock \"clk\" has Internal fmax of 317.36 MHz between source register \"select4_1:inst3\|q\[6\]\" and destination register \"counter8:inst1\|q\[6\]~reg0\" (period= 3.151 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.832 ns + Longest register register " "Info: + Longest register to register delay is 0.832 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns select4_1:inst3\|q\[6\] 1 REG LCFF_X26_Y6_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y6_N31; Fanout = 2; REG Node = 'select4_1:inst3\|q\[6\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { select4_1:inst3|q[6] } "NODE_NAME" } } { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.366 ns) 0.832 ns counter8:inst1\|q\[6\]~reg0 2 REG LCFF_X26_Y6_N23 3 " "Info: 2: + IC(0.466 ns) + CELL(0.366 ns) = 0.832 ns; Loc. = LCFF_X26_Y6_N23; Fanout = 3; REG Node = 'counter8:inst1\|q\[6\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.832 ns" { select4_1:inst3|q[6] counter8:inst1|q[6]~reg0 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 43.99 % ) " "Info: Total cell delay = 0.366 ns ( 43.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.466 ns ( 56.01 % ) " "Info: Total interconnect delay = 0.466 ns ( 56.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.832 ns" { select4_1:inst3|q[6] counter8:inst1|q[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.832 ns" { select4_1:inst3|q[6] counter8:inst1|q[6]~reg0 } { 0.000ns 0.466ns } { 0.000ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.105 ns - Smallest " "Info: - Smallest clock skew is -2.105 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.349 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns counter8:inst1\|q\[6\]~reg0 3 REG LCFF_X26_Y6_N23 3 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X26_Y6_N23; Fanout = 3; REG Node = 'counter8:inst1\|q\[6\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.238 ns" { clk~clkctrl counter8:inst1|q[6]~reg0 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.349 ns" { clk clk~clkctrl counter8:inst1|q[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.349 ns" { clk clk~combout clk~clkctrl counter8:inst1|q[6]~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.454 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 4.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.787 ns) 2.583 ns clk_div:inst\|clk_temp 3 REG LCFF_X1_Y6_N29 3 " "Info: 3: + IC(0.685 ns) + CELL(0.787 ns) = 2.583 ns; Loc. = LCFF_X1_Y6_N29; Fanout = 3; REG Node = 'clk_div:inst\|clk_temp'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.472 ns" { clk~clkctrl clk_div:inst|clk_temp } "NODE_NAME" } } { "clk_div.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/clk_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.633 ns) + CELL(0.000 ns) 3.216 ns clk_div:inst\|clk_temp~clkctrl 4 COMB CLKCTRL_G0 3 " "Info: 4: + IC(0.633 ns) + CELL(0.000 ns) = 3.216 ns; Loc. = CLKCTRL_G0; Fanout = 3; COMB Node = 'clk_div:inst\|clk_temp~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.633 ns" { clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl } "NODE_NAME" } } { "clk_div.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/clk_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 4.454 ns select4_1:inst3\|q\[6\] 5 REG LCFF_X26_Y6_N31 2 " "Info: 5: + IC(0.701 ns) + CELL(0.537 ns) = 4.454 ns; Loc. = LCFF_X26_Y6_N31; Fanout = 2; REG Node = 'select4_1:inst3\|q\[6\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.238 ns" { clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[6] } "NODE_NAME" } } { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 51.93 % ) " "Info: Total cell delay = 2.313 ns ( 51.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.141 ns ( 48.07 % ) " "Info: Total interconnect delay = 2.141 ns ( 48.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.454 ns" { clk clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.454 ns" { clk clk~combout clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[6] } { 0.000ns 0.000ns 0.122ns 0.685ns 0.633ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.349 ns" { clk clk~clkctrl counter8:inst1|q[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.349 ns" { clk clk~combout clk~clkctrl counter8:inst1|q[6]~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.454 ns" { clk clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.454 ns" { clk clk~combout clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[6] } { 0.000ns 0.000ns 0.122ns 0.685ns 0.633ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.832 ns" { select4_1:inst3|q[6] counter8:inst1|q[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.832 ns" { select4_1:inst3|q[6] counter8:inst1|q[6]~reg0 } { 0.000ns 0.466ns } { 0.000ns 0.366ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.349 ns" { clk clk~clkctrl counter8:inst1|q[6]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.349 ns" { clk clk~combout clk~clkctrl counter8:inst1|q[6]~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.454 ns" { clk clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[6] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.454 ns" { clk clk~combout clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[6] } { 0.000ns 0.000ns 0.122ns 0.685ns 0.633ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "counter8:inst1\|q\[7\]~reg0 en clk 5.253 ns register " "Info: tsu for register \"counter8:inst1\|q\[7\]~reg0\" (data pin = \"en\", clock pin = \"clk\") is 5.253 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.638 ns + Longest pin register " "Info: + Longest pin to register delay is 7.638 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns en 1 PIN PIN_65 2 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_65; Fanout = 2; PIN Node = 'en'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 272 184 352 288 "en" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.387 ns) + CELL(0.393 ns) 6.630 ns counter8:inst1\|q\[0\]~115 2 COMB LCCOMB_X26_Y6_N10 2 " "Info: 2: + IC(5.387 ns) + CELL(0.393 ns) = 6.630 ns; Loc. = LCCOMB_X26_Y6_N10; Fanout = 2; COMB Node = 'counter8:inst1\|q\[0\]~115'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.780 ns" { en counter8:inst1|q[0]~115 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 6.701 ns counter8:inst1\|q\[1\]~116 3 COMB LCCOMB_X26_Y6_N12 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 6.701 ns; Loc. = LCCOMB_X26_Y6_N12; Fanout = 2; COMB Node = 'counter8:inst1\|q\[1\]~116'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { counter8:inst1|q[0]~115 counter8:inst1|q[1]~116 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 6.860 ns counter8:inst1\|q\[2\]~117 4 COMB LCCOMB_X26_Y6_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 6.860 ns; Loc. = LCCOMB_X26_Y6_N14; Fanout = 2; COMB Node = 'counter8:inst1\|q\[2\]~117'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { counter8:inst1|q[1]~116 counter8:inst1|q[2]~117 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 6.931 ns counter8:inst1\|q\[3\]~118 5 COMB LCCOMB_X26_Y6_N16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 6.931 ns; Loc. = LCCOMB_X26_Y6_N16; Fanout = 2; COMB Node = 'counter8:inst1\|q\[3\]~118'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { counter8:inst1|q[2]~117 counter8:inst1|q[3]~118 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.002 ns counter8:inst1\|q\[4\]~119 6 COMB LCCOMB_X26_Y6_N18 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 7.002 ns; Loc. = LCCOMB_X26_Y6_N18; Fanout = 2; COMB Node = 'counter8:inst1\|q\[4\]~119'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { counter8:inst1|q[3]~118 counter8:inst1|q[4]~119 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.073 ns counter8:inst1\|q\[5\]~120 7 COMB LCCOMB_X26_Y6_N20 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 7.073 ns; Loc. = LCCOMB_X26_Y6_N20; Fanout = 2; COMB Node = 'counter8:inst1\|q\[5\]~120'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { counter8:inst1|q[4]~119 counter8:inst1|q[5]~120 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.144 ns counter8:inst1\|q\[6\]~121 8 COMB LCCOMB_X26_Y6_N22 1 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 7.144 ns; Loc. = LCCOMB_X26_Y6_N22; Fanout = 1; COMB Node = 'counter8:inst1\|q\[6\]~121'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { counter8:inst1|q[5]~120 counter8:inst1|q[6]~121 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 7.554 ns counter8:inst1\|q\[7\]~107 9 COMB LCCOMB_X26_Y6_N24 1 " "Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 7.554 ns; Loc. = LCCOMB_X26_Y6_N24; Fanout = 1; COMB Node = 'counter8:inst1\|q\[7\]~107'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { counter8:inst1|q[6]~121 counter8:inst1|q[7]~107 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.638 ns counter8:inst1\|q\[7\]~reg0 10 REG LCFF_X26_Y6_N25 2 " "Info: 10: + IC(0.000 ns) + CELL(0.084 ns) = 7.638 ns; Loc. = LCFF_X26_Y6_N25; Fanout = 2; REG Node = 'counter8:inst1\|q\[7\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { counter8:inst1|q[7]~107 counter8:inst1|q[7]~reg0 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.251 ns ( 29.47 % ) " "Info: Total cell delay = 2.251 ns ( 29.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.387 ns ( 70.53 % ) " "Info: Total interconnect delay = 5.387 ns ( 70.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.638 ns" { en counter8:inst1|q[0]~115 counter8:inst1|q[1]~116 counter8:inst1|q[2]~117 counter8:inst1|q[3]~118 counter8:inst1|q[4]~119 counter8:inst1|q[5]~120 counter8:inst1|q[6]~121 counter8:inst1|q[7]~107 counter8:inst1|q[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.638 ns" { en en~combout counter8:inst1|q[0]~115 counter8:inst1|q[1]~116 counter8:inst1|q[2]~117 counter8:inst1|q[3]~118 counter8:inst1|q[4]~119 counter8:inst1|q[5]~120 counter8:inst1|q[6]~121 counter8:inst1|q[7]~107 counter8:inst1|q[7]~reg0 } { 0.000ns 0.000ns 5.387ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.850ns 0.393ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.349 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns counter8:inst1\|q\[7\]~reg0 3 REG LCFF_X26_Y6_N25 2 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X26_Y6_N25; Fanout = 2; REG Node = 'counter8:inst1\|q\[7\]~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.238 ns" { clk~clkctrl counter8:inst1|q[7]~reg0 } "NODE_NAME" } } { "counter8.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/counter8.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.349 ns" { clk clk~clkctrl counter8:inst1|q[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.349 ns" { clk clk~combout clk~clkctrl counter8:inst1|q[7]~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.638 ns" { en counter8:inst1|q[0]~115 counter8:inst1|q[1]~116 counter8:inst1|q[2]~117 counter8:inst1|q[3]~118 counter8:inst1|q[4]~119 counter8:inst1|q[5]~120 counter8:inst1|q[6]~121 counter8:inst1|q[7]~107 counter8:inst1|q[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.638 ns" { en en~combout counter8:inst1|q[0]~115 counter8:inst1|q[1]~116 counter8:inst1|q[2]~117 counter8:inst1|q[3]~118 counter8:inst1|q[4]~119 counter8:inst1|q[5]~120 counter8:inst1|q[6]~121 counter8:inst1|q[7]~107 counter8:inst1|q[7]~reg0 } { 0.000ns 0.000ns 5.387ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.850ns 0.393ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.349 ns" { clk clk~clkctrl counter8:inst1|q[7]~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.349 ns" { clk clk~combout clk~clkctrl counter8:inst1|q[7]~reg0 } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qm\[2\] select4_1:inst3\|q\[0\] 9.931 ns register " "Info: tco from clock \"clk\" to destination pin \"qm\[2\]\" through register \"select4_1:inst3\|q\[0\]\" is 9.931 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.454 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 72 -336 -168 88 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.685 ns) + CELL(0.787 ns) 2.583 ns clk_div:inst\|clk_temp 3 REG LCFF_X1_Y6_N29 3 " "Info: 3: + IC(0.685 ns) + CELL(0.787 ns) = 2.583 ns; Loc. = LCFF_X1_Y6_N29; Fanout = 3; REG Node = 'clk_div:inst\|clk_temp'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.472 ns" { clk~clkctrl clk_div:inst|clk_temp } "NODE_NAME" } } { "clk_div.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/clk_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.633 ns) + CELL(0.000 ns) 3.216 ns clk_div:inst\|clk_temp~clkctrl 4 COMB CLKCTRL_G0 3 " "Info: 4: + IC(0.633 ns) + CELL(0.000 ns) = 3.216 ns; Loc. = CLKCTRL_G0; Fanout = 3; COMB Node = 'clk_div:inst\|clk_temp~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.633 ns" { clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl } "NODE_NAME" } } { "clk_div.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/clk_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 4.454 ns select4_1:inst3\|q\[0\] 5 REG LCFF_X26_Y6_N9 10 " "Info: 5: + IC(0.701 ns) + CELL(0.537 ns) = 4.454 ns; Loc. = LCFF_X26_Y6_N9; Fanout = 10; REG Node = 'select4_1:inst3\|q\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.238 ns" { clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[0] } "NODE_NAME" } } { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.313 ns ( 51.93 % ) " "Info: Total cell delay = 2.313 ns ( 51.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.141 ns ( 48.07 % ) " "Info: Total interconnect delay = 2.141 ns ( 48.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.454 ns" { clk clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.454 ns" { clk clk~combout clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[0] } { 0.000ns 0.000ns 0.122ns 0.685ns 0.633ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.227 ns + Longest register pin " "Info: + Longest register to pin delay is 5.227 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns select4_1:inst3\|q\[0\] 1 REG LCFF_X26_Y6_N9 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y6_N9; Fanout = 10; REG Node = 'select4_1:inst3\|q\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { select4_1:inst3|q[0] } "NODE_NAME" } } { "select4_1.vhd" "" { Text "E:/谢蓓雷的毕业设计/qpsktiao/select4_1.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.429 ns) + CELL(2.798 ns) 5.227 ns qm\[2\] 2 PIN PIN_135 0 " "Info: 2: + IC(2.429 ns) + CELL(2.798 ns) = 5.227 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'qm\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.227 ns" { select4_1:inst3|q[0] qm[2] } "NODE_NAME" } } { "qpsktiao.bdf" "" { Schematic "E:/谢蓓雷的毕业设计/qpsktiao/qpsktiao.bdf" { { 472 360 536 488 "qm\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 53.53 % ) " "Info: Total cell delay = 2.798 ns ( 53.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.429 ns ( 46.47 % ) " "Info: Total interconnect delay = 2.429 ns ( 46.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.227 ns" { select4_1:inst3|q[0] qm[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.227 ns" { select4_1:inst3|q[0] qm[2] } { 0.000ns 2.429ns } { 0.000ns 2.798ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.454 ns" { clk clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.454 ns" { clk clk~combout clk~clkctrl clk_div:inst|clk_temp clk_div:inst|clk_temp~clkctrl select4_1:inst3|q[0] } { 0.000ns 0.000ns 0.122ns 0.685ns 0.633ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.227 ns" { select4_1:inst3|q[0] qm[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.227 ns" { select4_1:inst3|q[0] qm[2] } { 0.000ns 2.429ns } { 0.000ns 2.798ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}