qpsktiao.tan.rpt

用VHDL语言实现QPSK调制功能和解调功能,

; N/A           ; None        ; -2.000 ns ; start ; seri_2:inst4|q[0]        ; clk      ;
; N/A           ; None        ; -2.000 ns ; start ; seri_2:inst4|q[1]        ; clk      ;
; N/A           ; None        ; -2.000 ns ; start ; seri_2:inst4|xx[1]       ; clk      ;
; N/A           ; None        ; -4.126 ns ; en    ; counter8:inst1|q[0]~reg0 ; clk      ;
; N/A           ; None        ; -4.509 ns ; en    ; counter8:inst1|q[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.580 ns ; en    ; counter8:inst1|q[2]~reg0 ; clk      ;
; N/A           ; None        ; -4.739 ns ; en    ; counter8:inst1|q[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.810 ns ; en    ; counter8:inst1|q[4]~reg0 ; clk      ;
; N/A           ; None        ; -4.881 ns ; en    ; counter8:inst1|q[5]~reg0 ; clk      ;
; N/A           ; None        ; -4.952 ns ; en    ; counter8:inst1|q[6]~reg0 ; clk      ;
; N/A           ; None        ; -5.023 ns ; en    ; counter8:inst1|q[7]~reg0 ; clk      ;
+---------------+-------------+-----------+-------+--------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri May 09 10:39:16 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qpsktiao -c qpsktiao --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "fenpin:inst2|count[2]" as buffer
    Info: Detected ripple clock "clk_div:inst|clk_temp" as buffer
Info: Clock "clk" has Internal fmax of 317.36 MHz between source register "select4_1:inst3|q[6]" and destination register "counter8:inst1|q[6]~reg0" (period= 3.151 ns)
    Info: + Longest register to register delay is 0.832 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y6_N31; Fanout = 2; REG Node = 'select4_1:inst3|q[6]'
        Info: 2: + IC(0.466 ns) + CELL(0.366 ns) = 0.832 ns; Loc. = LCFF_X26_Y6_N23; Fanout = 3; REG Node = 'counter8:inst1|q[6]~reg0'
        Info: Total cell delay = 0.366 ns ( 43.99 % )
        Info: Total interconnect delay = 0.466 ns ( 56.01 % )
    Info: - Smallest clock skew is -2.105 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.349 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X26_Y6_N23; Fanout = 3; REG Node = 'counter8:inst1|q[6]~reg0'
            Info: Total cell delay = 1.526 ns ( 64.96 % )
            Info: Total interconnect delay = 0.823 ns ( 35.04 % )
        Info: - Longest clock path from clock "clk" to source register is 4.454 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.685 ns) + CELL(0.787 ns) = 2.583 ns; Loc. = LCFF_X1_Y6_N29; Fanout = 3; REG Node = 'clk_div:inst|clk_temp'
            Info: 4: + IC(0.633 ns) + CELL(0.000 ns) = 3.216 ns; Loc. = CLKCTRL_G0; Fanout = 3; COMB Node = 'clk_div:inst|clk_temp~clkctrl'
            Info: 5: + IC(0.701 ns) + CELL(0.537 ns) = 4.454 ns; Loc. = LCFF_X26_Y6_N31; Fanout = 2; REG Node = 'select4_1:inst3|q[6]'
            Info: Total cell delay = 2.313 ns ( 51.93 % )
            Info: Total interconnect delay = 2.141 ns ( 48.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "counter8:inst1|q[7]~reg0" (data pin = "en", clock pin = "clk") is 5.253 ns
    Info: + Longest pin to register delay is 7.638 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_65; Fanout = 2; PIN Node = 'en'
        Info: 2: + IC(5.387 ns) + CELL(0.393 ns) = 6.630 ns; Loc. = LCCOMB_X26_Y6_N10; Fanout = 2; COMB Node = 'counter8:inst1|q[0]~115'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 6.701 ns; Loc. = LCCOMB_X26_Y6_N12; Fanout = 2; COMB Node = 'counter8:inst1|q[1]~116'
        Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 6.860 ns; Loc. = LCCOMB_X26_Y6_N14; Fanout = 2; COMB Node = 'counter8:inst1|q[2]~117'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 6.931 ns; Loc. = LCCOMB_X26_Y6_N16; Fanout = 2; COMB Node = 'counter8:inst1|q[3]~118'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 7.002 ns; Loc. = LCCOMB_X26_Y6_N18; Fanout = 2; COMB Node = 'counter8:inst1|q[4]~119'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 7.073 ns; Loc. = LCCOMB_X26_Y6_N20; Fanout = 2; COMB Node = 'counter8:inst1|q[5]~120'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 7.144 ns; Loc. = LCCOMB_X26_Y6_N22; Fanout = 1; COMB Node = 'counter8:inst1|q[6]~121'
        Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 7.554 ns; Loc. = LCCOMB_X26_Y6_N24; Fanout = 1; COMB Node = 'counter8:inst1|q[7]~107'
        Info: 10: + IC(0.000 ns) + CELL(0.084 ns) = 7.638 ns; Loc. = LCFF_X26_Y6_N25; Fanout = 2; REG Node = 'counter8:inst1|q[7]~reg0'
        Info: Total cell delay = 2.251 ns ( 29.47 % )
        Info: Total interconnect delay = 5.387 ns ( 70.53 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.349 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X26_Y6_N25; Fanout = 2; REG Node = 'counter8:inst1|q[7]~reg0'
        Info: Total cell delay = 1.526 ns ( 64.96 % )
        Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: tco from clock "clk" to destination pin "qm[2]" through register "select4_1:inst3|q[0]" is 9.931 ns
    Info: + Longest clock path from clock "clk" to source register is 4.454 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.685 ns) + CELL(0.787 ns) = 2.583 ns; Loc. = LCFF_X1_Y6_N29; Fanout = 3; REG Node = 'clk_div:inst|clk_temp'
        Info: 4: + IC(0.633 ns) + CELL(0.000 ns) = 3.216 ns; Loc. = CLKCTRL_G0; Fanout = 3; COMB Node = 'clk_div:inst|clk_temp~clkctrl'
        Info: 5: + IC(0.701 ns) + CELL(0.537 ns) = 4.454 ns; Loc. = LCFF_X26_Y6_N9; Fanout = 10; REG Node = 'select4_1:inst3|q[0]'
        Info: Total cell delay = 2.313 ns ( 51.93 % )
        Info: Total interconnect delay = 2.141 ns ( 48.07 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.227 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y6_N9; Fanout = 10; REG Node = 'select4_1:inst3|q[0]'
        Info: 2: + IC(2.429 ns) + CELL(2.798 ns) = 5.227 ns; Loc. = PIN_135; Fanout = 0; PIN Node = 'qm[2]'
        Info: Total cell delay = 2.798 ns ( 53.53 % )
        Info: Total interconnect delay = 2.429 ns ( 46.47 % )
Info: th for register "seri_2:inst4|xx[0]" (data pin = "x", clock pin = "clk") is -0.856 ns
    Info: + Longest clock path from clock "clk" to destination register is 4.754 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.701 ns) + CELL(0.787 ns) = 2.599 ns; Loc. = LCFF_X27_Y6_N25; Fanout = 3; REG Node = 'fenpin:inst2|count[2]'
        Info: 4: + IC(0.886 ns) + CELL(0.000 ns) = 3.485 ns; Loc. = CLKCTRL_G4; Fanout = 7; COMB Node = 'fenpin:inst2|count[2]~clkctrl'
        Info: 5: + IC(0.732 ns) + CELL(0.537 ns) = 4.754 ns; Loc. = LCFF_X21_Y13_N7; Fanout = 2; REG Node = 'seri_2:inst4|xx[0]'
        Info: Total cell delay = 2.313 ns ( 48.65 % )
        Info: Total interconnect delay = 2.441 ns ( 51.35 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 5.876 ns
        Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_118; Fanout = 2; PIN Node = 'x'
        Info: 2: + IC(4.802 ns) + CELL(0.150 ns) = 5.792 ns; Loc. = LCCOMB_X21_Y13_N6; Fanout = 1; COMB Node = 'seri_2:inst4|xx[0]~161'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.876 ns; Loc. = LCFF_X21_Y13_N7; Fanout = 2; REG Node = 'seri_2:inst4|xx[0]'
        Info: Total cell delay = 1.074 ns ( 18.28 % )
        Info: Total interconnect delay = 4.802 ns ( 81.72 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Fri May 09 10:39:16 2008
    Info: Elapsed time: 00:00:01