bcdconv.map.eqn

BCD编码的Verilog HDL程序

--A1L02 is i21~9
A1L02_p1_out = EN & data_in[0];
A1L02_or_out = A1L02_p1_out;
A1L02 = A1L02_or_out;


--A1L71 is i18~11
A1L71_p1_out = EN & !data_in[2] & !data_in[1] & data_in[3];
A1L71_or_out = A1L71_p1_out;
A1L71 = A1L71_or_out;


--A1L81 is i19~18
A1L81_p1_out = EN & data_in[2] & data_in[1];
A1L81_p2_out = EN & data_in[2] & !data_in[3];
A1L81_or_out = A1L81_p1_out # A1L81_p2_out;
A1L81 = A1L81_or_out;


--A1L61 is i17~15
A1L61_p1_out = data_in[2] & data_in[3];
A1L61_p2_out = data_in[3] & data_in[1];
A1L61_or_out = A1L61_p1_out # A1L61_p2_out # !EN;
A1L61 = A1L61_or_out;


--A1L91 is i20~49
A1L91_p1_out = EN & data_in[2] & !data_in[1] & data_in[3];
A1L91_p2_out = EN & data_in[1] & !data_in[3];
A1L91_or_out = A1L91_p1_out # A1L91_p2_out;
A1L91 = A1L91_or_out;


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~GND~1 is ~GND~1
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;


--~GND~2 is ~GND~2
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;


--data_in[3] is data_in[3]
--operation mode is input

data_in[3] = INPUT();


--data_in[2] is data_in[2]
--operation mode is input

data_in[2] = INPUT();


--data_in[1] is data_in[1]
--operation mode is input

data_in[1] = INPUT();


--data_in[0] is data_in[0]
--operation mode is input

data_in[0] = INPUT();


--EN is EN
--operation mode is input

EN = INPUT();


--data_out[7] is data_out[7]
--operation mode is output

data_out[7] = OUTPUT(~GND~0);


--data_out[6] is data_out[6]
--operation mode is output

data_out[6] = OUTPUT(~GND~1);


--data_out[5] is data_out[5]
--operation mode is output

data_out[5] = OUTPUT(~GND~2);


--data_out[0] is data_out[0]
--operation mode is output

data_out[0] = OUTPUT(A1L02);


--data_out[3] is data_out[3]
--operation mode is output

data_out[3] = OUTPUT(A1L71);


--data_out[2] is data_out[2]
--operation mode is output

data_out[2] = OUTPUT(A1L81);


--data_out[4] is data_out[4]
--operation mode is output

data_out[4] = OUTPUT(A1L61);


--data_out[1] is data_out[1]
--operation mode is output

data_out[1] = OUTPUT(A1L91);