bcdconv.map.qmsg

BCD编码的Verilog HDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 13 20:04:43 2005 " "Info: Processing started: Sun Mar 13 20:04:43 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --lower_priority --import_settings_files=on --export_settings_files=off BCDconv -c BCDconv " "Info: Command: quartus_map --lower_priority --import_settings_files=on --export_settings_files=off BCDconv -c BCDconv" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BCDconv.v 1 1 " "Info: Found 1 design units and 1 entities in source file BCDconv.v" { { "Info" "ISGN_ENTITY_NAME" "1 BCDconv " "Info: Found entity 1: BCDconv" {  } { { "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" "BCDconv" "" { Text "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "data_out\[7\] GND " "Warning: Pin data_out\[7\] stuck at GND" {  } { { "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" "" "" { Text "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" 14 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_out\[6\] GND " "Warning: Pin data_out\[6\] stuck at GND" {  } { { "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" "" "" { Text "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" 14 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "data_out\[5\] GND " "Warning: Pin data_out\[5\] stuck at GND" {  } { { "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" "" "" { Text "D:/工作目录/2_人民邮电刘浩/选题3--CPLD实例导航/文档目录/第3章 ing/BCDconv/BCDconv.v" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "21 " "Info: Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "8 " "Info: Implemented 8 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 13 20:04:45 2005 " "Info: Processing ended: Sun Mar 13 20:04:45 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}