bcdconv.eda.qmsg

BCD编码的Verilog HDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 13 18:31:25 2005 " "Info: Processing started: Sun Mar 13 18:31:25 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --lower_priority --import_settings_files=on --export_settings_files=off BCDconv -c BCDconv " "Info: Command: quartus_eda --lower_priority --import_settings_files=on --export_settings_files=off BCDconv -c BCDconv" {  } {  } 0}
{ "Warning" "WQNETO_NO_OUTPUT_FILES" "" "Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script." {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 13 18:31:25 2005 " "Info: Processing ended: Sun Mar 13 18:31:25 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}