bcdconv.v

来自「BCD编码的Verilog HDL程序」· Verilog 代码 · 共 45 行

//
// 
//-----------------------------------------------------------------------------------
//十进制数值的BCD编码转换
//输入:data_in,输入数值，以二进制形式表示，输入位宽为4比特
//	   EN,变换输出使能信号，高电平有效
//输出:data_out,BCD编码输出，采用非压缩编码，数据位宽为8比特
//-----------------------------------------------------------------------------------

module BCDconv (data_in ,EN ,data_out );

input [3:0] data_in ;
input EN ;
output [7:0] data_out ;
reg [7:0] data_out ;



	always @(data_in or EN )
	begin
		data_out = {8{1'b0}};
		if (EN == 1)
		begin
			case (data_in [3:1]) 
				3'b000 : data_out [7:1] = 7'b0000000;
				3'b001 : data_out [7:1] = 7'b0000001;
				3'b010 : data_out [7:1] = 7'b0000010;
				3'b011 : data_out [7:1] = 7'b0000011;
				3'b100 : data_out [7:1] = 7'b0000100;
				3'b101 : data_out [7:1] = 7'b0001000;
				3'b110 : data_out [7:1] = 7'b0001001;
				3'b111 : data_out [7:1] = 7'b0001010;
				default : data_out [7:1] = {7{1'b0}};
			endcase
			data_out [0] = data_in [0];
		end
		else
		begin
			//data_out [3:0] = data_in[3:0];
			data_out [4] = 1'b1;
		end
	end

endmodule